1. ASIP Architecture for Future Wireless Systems: Flexibility and Customization Joseph Cavallaro and Predrag Radosavljevic Rice University Center for Multimedia Communication ECE Department, Houston, Texas USA WWRF11 Meeting 10-11 June 2004

2. Page 2 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway Processors in Future Wireless Systems  Future generations of mobile handsets:  High speed and low power  Flexibility  Traditional approaches: ASIC and DSP processors  ASIC drawbacks:  No flexibility: family of ASICs are needed  High probability of design errors, high design cost  DSP drawbacks:  Not optimized for a specific application  Often limited instruction and data level parallelism

3. Page 3 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway Processors in Future Wireless Systems  ASIPs (Application Specific Instruction Processors):  Excellent tradeoff between efficiency of ASICs and flexibility of DSPs

4. Page 4 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway ASIP Architecture Design  Flexible processors for mobile handsets:  Different modifications of wireless base-band algorithms (processing in slow/fast fading, low/high scattering environments)  Support for evolution of standards (3GPP, 4G, 802.11x, WiFi, etc)  Efficient processors to achieve high-demanding real time requirements:  Customized architecture is needed  Extension of ASIP instruction set with application-specific operations

5. Page 5 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway ASIP Architecture Based on TTA  TTA: Transport Triggered Architecture  Operations are triggered by data transport  Automatic hardware design flow:  Software environment enables reconfigurable implementation  Retargetable compiler  Conversion from C/C++ code of application to gate level processor design  Fast processor design  Automatic search for optimal (performance/cost) processor  VHDL representation of processor core obtained by software tool

6. Page 6 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway ASIP Architecture Based on TTA  Flexible architecture  No limitations to add new FUs, buses, registers  Customizable architecture  Implementation of Special Function Units (SFUs)  Instruction and data level parallelism  Efficient and parallel data flow  Sub-word parallelism by implementing appropriate SFU

7. Page 7 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway General Structure of TTA  VLIW architecture principle  Expanded compiler characteristics  Software specification of data transports  Simpler architecture than traditional VLIW  Large flexibility  Independent design of interconnection network and FUs  Easy to add/remove FUs and RFs  Software design environment

8. Page 8 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway ASIP Design Flow  Fast and efficient hardware/software co-design  Modified MOVE tool: exploration for optimal TTA processor with SFUs  MOVEGen tool: conversion of processor description into VHDL representation  Xilinx ISE Foundation for fast FPGA prototyping  Mentor Graphics tools: generation of processor layout

9. Page 9 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway Our Application: MIMO Downlink Equalization  Physical layer of mobile handset in MIMO downlink  ASIP architecture based on TTA  Flexible architecture solution for different modifications of channel equalization algorithm  Highly optimized for the most computationally complex version of channel equalization

10. Page 10 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway High Computational Complexity  Number of operations per chip in one second  Workload varies with velocity and number of channel multipaths  Required processor flexibility  Higher workload than typical operation count specification for TI C5x DSP (widely used in 2G mobile handsets)

11. Page 11 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway TTA Processor for Equalization  Customized processor  Application-specific SFUs for equalization  Area of approximately 140K Gates  Flexible design  Equalization in broad range of environments  Dynamic power dissipation: 32mW – 54 mW  Minimum clock frequency to achieve real time: 42MHz – 109MHz Processor core including data memory

12. Page 12 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway SFU Example: Complex Multiplication  Reduction of data transports between FUs  Less number of buses and smaller interconnection network  Smaller instruction word  Instruction and data parallelism placed inside CXMUL Real multipliers Complex multiplier

13. Page 13 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway Gate Level CMOS Synthesis  Mentor Graphics Tools  Leonardo Spectrum for low level synthesis  IC Station for automatic layout generation  CMOS library of logic cells  Customized equalizer with user detection  Included library of SFUs  Synthesis estimate of processor core: 182,887 gates

14. Page 14 WWRF11 Meeting, 10-11 June 2004, Oslo, Norway Conclusions  ASIP architecture based on TTA for future mobile handsets  Same efficiency as ASIC while keeping flexibility  Customization  SFUs for application specific operations  Optimization of architecture  Reduction of power dissipation and area while achieving speedup  Interaction between hardware implementation and software environment  Fast and efficient design flow  Easy to fix design errors