1. IEEE NSS & MIC, Norfolk, Virginia, November 2002 1 Triggering on Particle Types: Calorimeter and Muon Based Triggers Sridhara Dasu Department of Physics University of Wisconsin-Madison http://www.hep.wisc.edu/~dasu/public/DasuIEEETrg.pdf Many slides stolen from: Sergio Cittolin, James Linnemann, and Wesley Smith

2. IEEE NSS & MIC, Norfolk, Virginia, November 2002 2ContentsContents Calorimeter Triggers Electrons, Photons,  -leptons and Jets Global energy triggers Energy clustering algorithms Muon Triggers Pattern matching Minimum ionizing signal Electrons and Muons Track Matching Specific implementation examples e+e- (BaBar) e-p (ZEUS) and Fixed target () p-pbar (CDF, D0, ATLAS, CMS) Technologies: ASICs, FPGAs,... Future We will discuss the triggers by examples that I am familiar with and in the process bring out the general themes.

3. IEEE NSS & MIC, Norfolk, Virginia, November 2002 3 e + -e - B Physics: BaBar, Belle Purpose of the trigger is to pass most (if not all) collision events Discriminate against beam- environment collisions TypeRate (Hz) Physics180 Cosmic100 Random20 Beam Background 1000-2000 Hardware trigger (L1) Tracks + Energy < 2.5 kHz Software trigger (L3) ~ 100 Hz to tape Remove background Prescale Bhabhas 2 Level Trigger

4. IEEE NSS & MIC, Norfolk, Virginia, November 2002 4 BaBar L1 Trigger Overview Calorimeter Trigger N-bit pattern of energy deposits in crystals Tagged by  angle Total  -map from 10 TPBs Used in combination with the track trigger Muon Trigger 3-bit pattern representing hit topology in the muon chambers (RPCs) Used for cosmic trigger Drift Chamber Trigger Track stubs P T discrimination Main trigger for BaBar

5. IEEE NSS & MIC, Norfolk, Virginia, November 2002 5 ZEUS QCD Physics Trigger on Electrons Jets, Missing E T Total E T

6. IEEE NSS & MIC, Norfolk, Virginia, November 2002 6 Hadron Collider Experiments: CDF, D0, ATLAS, CMS B Physics (10 GeV) 2-5 GeV particles 10 kHz (Tevatron) Specific Channels, Tracks + Separated vertices 1 MHz (LHC) - Hopeless for ATLAS, CMS Physics at EWSB scale (250 GeV) 115 < M higgs < 200 GeV Couplings to W (80), Z (91) Lepton P T ~ 40 GeV TeV scale supersymmetry Multiple leptons, jets and LSPs (missing P T ), P T < 100 GeV QCD Background Jet E T ~ 250 GeV Rate = 1 kHz (LHC), 0.01 Hz (Tevatron) Jet fluctuations  electron BG Decays of , k, B  muon BG Technical challenges 7,40 MHz input  fast processing 100 Hz output  physics selection Note: Divide by 100 for CDF,D0

7. IEEE NSS & MIC, Norfolk, Virginia, November 2002 7 Hadron Collider L1 Trigger Challenge Short timescales Large channel count Large rate reduction CDF,D0ZEUSATLAS,CMS Bunch crossing (ns)132 (396)9625 Decision latency (  s) 452,3 Channel count2000 8000 Rate reduction (kHz)2525 to 7,50100 to 0.540000 to 100 Faster, high density electronics with fancy algorithms

8. IEEE NSS & MIC, Norfolk, Virginia, November 2002 8 Overview : ZEUS Pipelined 3 level trigger Level-1 (Electronics) Calorimeter Trackers Level-2 (Processors) Calorimeter Trackers Level-3 (Software) Event Reconstruction

9. IEEE NSS & MIC, Norfolk, Virginia, November 2002 9 Overview : CDF Trigger

10. IEEE NSS & MIC, Norfolk, Virginia, November 2002 10 Overview : D0 Trigger 128 terms 50 Hz L2 100  s L1/Lum 4.2  s Framework 7 MHz input rate Data Data Log 7 kHz 1000 Hz L3 48+  ms 48 nodes

11. IEEE NSS & MIC, Norfolk, Virginia, November 2002 11 Overview : D0 Framework

12. IEEE NSS & MIC, Norfolk, Virginia, November 2002 12 Overview : ATLAS & CMS Examples ATLAS CMS

13. IEEE NSS & MIC, Norfolk, Virginia, November 2002 13 ATLAS and CMS Strategy Complexity handled in software on CPUs

14. IEEE NSS & MIC, Norfolk, Virginia, November 2002 14ThemeTheme Level-1: Energy over threshold (BaBar, Belle, CDF, D0) to object identification (ZEUS, CDF, D0) to object isolation (ATLAS, CMS) Level-2: Custom processors (CDF, D0, ZEUS) to full readout after Level-1 (BaBar, CMS) We will talk only about Level-1 Calorimeter and Muon triggers More sophisticated algorithms possible at level-2, separated vertices for B physics, etc. are discussed in other talks.

15. IEEE NSS & MIC, Norfolk, Virginia, November 2002 15 Interaction of Particles with Matter

16. IEEE NSS & MIC, Norfolk, Virginia, November 2002 16 Projective Geometry Projective geometry is important ZEUS: Used complicated cable mapping and pattern searches to reduce fake rate ATLAS, CMS: Calorimeters are built projective Mapping with muon system: Important for isolation

17. IEEE NSS & MIC, Norfolk, Virginia, November 2002 17 D0 Muon System 

18. IEEE NSS & MIC, Norfolk, Virginia, November 2002 18 D0 Calorimeter Trigger

19. IEEE NSS & MIC, Norfolk, Virginia, November 2002 19 D0 Calorimeter Trigger

20. IEEE NSS & MIC, Norfolk, Virginia, November 2002 20 D0 Muon Trigger

21. IEEE NSS & MIC, Norfolk, Virginia, November 2002 21 D0 Muon Trigger

22. IEEE NSS & MIC, Norfolk, Virginia, November 2002 22 D0 Muon Trigger

23. IEEE NSS & MIC, Norfolk, Virginia, November 2002 23 ZEUS Calorimeter Trigger Electronics 16 Crates Trigger Encoder Cards, Adder Cards Identify and count objects over threshold Electrons, Jets Energy sums Geometry VME Crate Custom P2 & P3 bus ECL logic runs at 2x, i.e., 20 MHz, on TEC, Adder

24. IEEE NSS & MIC, Norfolk, Virginia, November 2002 24 Flash ADC EMC, HAC Analog input from calorimeter Digitize Characterize Sum Bussed backplane for transferring data to Adder Cards ZEUS Trigger Encoder Card Discrete ECL Logic

25. IEEE NSS & MIC, Norfolk, Virginia, November 2002 25 ZEUS Adder Card Object identification using pattern of energy deposition in the calorimeter.

26. IEEE NSS & MIC, Norfolk, Virginia, November 2002 26 CDF, D0 Level 2 CDF and D0 elected for simple level-1 but more sophisticated level-2 based on processors

27. IEEE NSS & MIC, Norfolk, Virginia, November 2002 27 Level-2 Crate

28. IEEE NSS & MIC, Norfolk, Virginia, November 2002 28 Level-2 Crate

29. IEEE NSS & MIC, Norfolk, Virginia, November 2002 29 Level-2 Data Bus

30. IEEE NSS & MIC, Norfolk, Virginia, November 2002 30 Level-2 Software

31. IEEE NSS & MIC, Norfolk, Virginia, November 2002 31 D0 Use of Generic L2 Processors

32. IEEE NSS & MIC, Norfolk, Virginia, November 2002 32 D0 L2 Trigger : Calorimeter Objects

33. IEEE NSS & MIC, Norfolk, Virginia, November 2002 33 D0 Level-2 Electron

34. IEEE NSS & MIC, Norfolk, Virginia, November 2002 34 D0 Level-2 Muon

35. IEEE NSS & MIC, Norfolk, Virginia, November 2002 35 D0 Level-2 Global Trigger

36. IEEE NSS & MIC, Norfolk, Virginia, November 2002 36 Calorimeter Geometry : CMS Example EB, EE, HB, HE map to 18 RCT crates Provide e/  and jet,  E T triggers

37. IEEE NSS & MIC, Norfolk, Virginia, November 2002 37 Trigger Mapping: CMS Example

38. IEEE NSS & MIC, Norfolk, Virginia, November 2002 38 CMS ECAL Front-end Electronics

39. IEEE NSS & MIC, Norfolk, Virginia, November 2002 39 ECAL Front-end Boards Serves one trigger tower 5x5 crystals Trigger Primitives: BCID, Energy, FG

40. IEEE NSS & MIC, Norfolk, Virginia, November 2002 40 ECAL Frontend ASICs E T sum for trigger tower 1-bit characterizing fine-grain energy deposit profile (FG) One ASIC but two personalities Final Algorithms in ASICs (0.25  Rad. Hard) Prototypes using FPGAs Gigabit optical to surface Trigger Primitives DAQ Different chips but similar output for HCAL

41. IEEE NSS & MIC, Norfolk, Virginia, November 2002 41SynchronizationSynchronization

42. 42 CMS Electron/Photon Algorithm Limit region of interest to minimum possible

43. IEEE NSS & MIC, Norfolk, Virginia, November 2002 43  / Jet Algorithm Reduce amount of data at each level to minimum needed

44. IEEE NSS & MIC, Norfolk, Virginia, November 2002 44 Missing / Total E T Algorithm 20 o 0o0o 40 o 360 o …… -5 5 0   E T 18 E x 18 E y 18 ET2ET2 Ex2Ex2 Ey2Ey2 ET1ET1 Ex1Ex1 Ey1Ey1 ETET ME T Strip E T sum over all  LUT For sums E T scale LSB (quantization) ~ 1 GeV is used  = 20 o used instead of HCAL tower size:  = 5 o

45. IEEE NSS & MIC, Norfolk, Virginia, November 2002 45 CMS Tower Level Memory LUT Lookup table for arbitrary nonlinear transform - including making E+H and H/E 8-bit nonlinear EM E T 8-bit nonlinear HD E T 1-bit EM fine-grain bit 7-bit linear E T 9-bit linear E T 1-bit Activity 1-bit H/E, FG Veto Electron Jet /  Fully programmable LUT, Current default values: - Electron scale: 0.5 GeV LSB, E max =63.5 GeV - Veto: OR of fine-grain veto and H / E < 5% - Jet /  scale (E+H): 1.0 GeV LSB, E max =511 GeV - Jet energy (12x12 tower sum), E max =1 TeV - Activity level for  pattern: E > 2 GeV, H > 4 GeV

46. IEEE NSS & MIC, Norfolk, Virginia, November 2002 46 160 MHz point to point backplane (prototype tested) 18 Clock&Control (prototype tested), 126 Electron ID (prototype tested), 18 Jet/Summary Cards -- all cards operate @ 160 MHz Use 5 Custom Gate-Array 160 MHz GaAs Vitesse Digital ASICs Phase, Adder, Boundary Scan, Electron Isolation, Sort (manufactured) CMS Calorimeter Trigger Crate Spares not included* Data from calorimeter FE on Cu links @ 1.2 Gbaud Into 126* rear Receiver CardsInto 126* rear Receiver Cards Prototype tested w/ ASICsPrototype tested w/ ASICs Backplane links fix the algorithm

47. IEEE NSS & MIC, Norfolk, Virginia, November 2002 47 CMS Regional Calorimeter Trigger Prototypes Clock and Control Card Fans out 160 MHz clock & adjusts phase to all boards Clock delay adjust DC-DC Converters

48. IEEE NSS & MIC, Norfolk, Virginia, November 2002 48 4 x 1.2 GB/s Copper Links Receiver mezzanine card Test Transmit mezzanine card Serial Link Test Cards 20 m 22 AWG Copper Cable, VGA Connector Results: Bit Error rate < 10 -15

49. IEEE NSS & MIC, Norfolk, Virginia, November 2002 49 Front Rear Std. VME Slots Crate & Backplane 160 MHz with 0.4 Tbit/sec dataflow Initial tests indicate good signal quality Designed to incorporate algorithm changes New Non-Isolated Electron, Tau & Jet Triggers Many data paths checked manually and with JTAG Note: we only have one RC and one EIDC for testing Plan: one complete fully tested crate for slice test VME Power Supply Custom Point-to-point Dataflow VME 48V externally supplied Custom Point-to-point Dataflow

50. IEEE NSS & MIC, Norfolk, Virginia, November 2002 50 CMS Receiver Card Top side with 1 of 8 mezzanine cards & 2 of 3 Adder ASICs DC-DC Adder mezz link cards BSCAN ASICs PHASE ASICs MLUs Bottom side with all Phase & Boundary Scan ASICs Full featured final prototype board is in test - ASIC testing successful. Continue to test all data paths - develop software etc. - FY2003 program Phase ASIC validated, BSCAN ASIC validated - all RC ASIC procurement now complete

51. IEEE NSS & MIC, Norfolk, Virginia, November 2002 51 CMS RCT : Adder ASIC Key RCT technology Fast ASICs - compact design

52. IEEE NSS & MIC, Norfolk, Virginia, November 2002 52 CMS Electron Isolation Card Full featured final prototype board is finished & under test. Electron ID & Sort ASICs tested by Vitesse before delivery In house testing fully validated SORT ASIC & mostly validated EISO ASIC - neighbor data requires multiple cards. SORT ASIC procurement complete Detailed tests of all data paths: FY2003 SORT ASICs EISO

53. IEEE NSS & MIC, Norfolk, Virginia, November 2002 53 Jet-Summary Card Being Assembled Electron/photon/muon info. SORT ASICs to find top four electron/photons Threshold for muon bits To GCT Region energies To cluster crate Absorbs HF functionality Reuses Receiver Mezzanine Card To cluster crate

54. IEEE NSS & MIC, Norfolk, Virginia, November 2002 54 CMS Global Calorimeter Trigger 1 GB/s serial inter-crate 3 GB/s serial backplane Cable backplane for flexibility

55. IEEE NSS & MIC, Norfolk, Virginia, November 2002 55 CMS Global Calorimeter Trigger Generic: Common CMS, ATLAS

56. IEEE NSS & MIC, Norfolk, Virginia, November 2002 56 CMS Muon Detectors

57. IEEE NSS & MIC, Norfolk, Virginia, November 2002 57 CMS Muon Overview ASICsFPGAs ASIC to FPGA FPGAs

58. IEEE NSS & MIC, Norfolk, Virginia, November 2002 58 CMS Muon Trigger Primitives Memory to store patterns Fast logic for matching FPGAs are ideal

59. IEEE NSS & MIC, Norfolk, Virginia, November 2002 59 CMS Muon Trigger Track Finder Memory to store patterns Fast logic for matching FPGAs are ideal Sort based on P T, Quality - keep loc. Combine at next level - match Sort again - Isolate? Top 4 highest P T and quality muons with location coord. Match with RPC Improve efficiency and quality

60. IEEE NSS & MIC, Norfolk, Virginia, November 2002 60 CMS Global Trigger

61. IEEE NSS & MIC, Norfolk, Virginia, November 2002 61 Trigger Flow : ATLAS Example

62. IEEE NSS & MIC, Norfolk, Virginia, November 2002 62 ATLAS Calorimeter Algorithms I

63. IEEE NSS & MIC, Norfolk, Virginia, November 2002 63 ATLAS Calorimeter Algorithms II

64. IEEE NSS & MIC, Norfolk, Virginia, November 2002 64 Calorimeter Trigger Overview : ATLAS Trigger Primitives Analog sum Receiver Quality cable plant Preprocessor ADC, Bunch-crossing LUT, sums Algorithm Implementation Jets,  E T, Missing E T e/ ,  /h FPGA Based Generic Processors (adopted for CMS GCT)

65. IEEE NSS & MIC, Norfolk, Virginia, November 2002 65 ATLAS Muon Trigger Detectors

66. IEEE NSS & MIC, Norfolk, Virginia, November 2002 66 ATLAS Muon Trigger

67. IEEE NSS & MIC, Norfolk, Virginia, November 2002 67 ATLAS Trigger Central Processor

68. IEEE NSS & MIC, Norfolk, Virginia, November 2002 68 CMS Calorimeter Trigger Rates: 2 x 10 33 cm -2 s -1 Selected Scenario: 5 kHz e/g, 5 kHz ,jets, 1 kHz combined, rest  Mock Trigger Table

69. IEEE NSS & MIC, Norfolk, Virginia, November 2002 69 CMS Calorimeter Physics Efficiency: 2 x 10 33 cm -2 s -1 Scenario: 5 kHz e/ , 5 kHz ,jets, 1 kHz comb, rest  No generator level cuts other than requiring trigger objects within calo. (  <5) or tracker (e,  ) acceptance

70. IEEE NSS & MIC, Norfolk, Virginia, November 2002 70 Improving L1 Efficiency for qqH SUSY higgs production in weak boson fusion Accompanied by jets in the forward direction Forward jet characteristics Lower jet E T, but potential beam background Strategy at level-1 Trigger on higgs decay products Decays to Z (ee,  ) or photons Low threshold electron/photon algorithm Decays to  Narrow jet tag - developed better algorithm (2000) Tag jets with location information Invisible decays (  ) Missing E T trigger by itself is not efficient Require two tag jets also Require  between the jets Decays to b jets (dominant but dirty mode) Four jet trigger including forward tag jets Require  between jets Exploit that central b jets must be back-to-back

71. IEEE NSS & MIC, Norfolk, Virginia, November 2002 71 Global L1 Trigger Algorithms

72. IEEE NSS & MIC, Norfolk, Virginia, November 2002 72 qqH to 2 b-jets + 2 tag jets b b q1q1 q2q2 02.5 5-5-2.5  Current Level-1 Trigger 4 jets anywhere in the detector Exploit separation of the tag jets in  4 jets with  > 3 Reduce 1-jet rate to compensate for new rate Rate reduction using event topology cuts Rapidity gap due to lack of color connection Require b-jets to be within the central detector AlgorithmEfficiency for M H =110 GeV Efficiency for M H =130 GeV 1, 2, 3, 4 jet triggers only 70%76% Additional  >3 cut 79% (+9%)82% (+8%)

73. IEEE NSS & MIC, Norfolk, Virginia, November 2002 73 High Level Trigger Strategy

74. IEEE NSS & MIC, Norfolk, Virginia, November 2002 74 Evolution of Level-1 Triggers Input Old - separate analog trigger sums + Cu cables New - on detector ADCs++ (radiation hard ASICs) trigger primitives formation, giga-bit fiber-optic transport Backplanes Old - VME Bus, FastBus New - Point-to-point high speed links, serial (1 to 3 GB/s) or parallel (160 MHz) Inter-crate links Old - Parallel differential ECL New - Serial 1.2 GB fiber or Cu links

75. IEEE NSS & MIC, Norfolk, Virginia, November 2002 75 Evolution of Level-1 Triggers Discrete Logic D0,CDF towers over thresholds + sums ZEUS sums + pattern logic for object ID ASICs CMS RCT - object identification isolation, sorting, fast adders FPGAs Almost everywhere - Generic processors