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3DCoB: A new design approach for Monolithic 3D Integrated Circuits H. Sarhan, S. Thuries, O. Billoint and F. Clermidy CEA-LETI, Minatec Campus, France ASPDAC 2014
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Outline Introduction Monolithic 3D ICs 3D Cell-on-Buffer (3DCoB) Design Flow Experimental Results Conclusions
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Introduction 3D monolithic integration is a methodology to fabricate the 3D IC where a second transistor layer is directly fabricated on top of the first one. The two transistors layers are connected through high-density inter-tier vias (about 100 times smaller compared to the TSVs).
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Monolithic 3D ICs Monolithic 3D integration approaches: Transistor-level (N/P) Gate-level (Cell on cell) Transistor-levelGate-level
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Monolithic 3D ICs Transistor-level (N/P) Gate-level (Cell-on-cell)
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3D Cell-on-Buffer (3DCoB) The main idea of the 3DCoB is to split the non-minimum drive 2D cells into a logical function stage and a drive stage. One tier contains the equivalent minimum-drive gate. The other tier contains a buffer to maintain the same driving capabilities of the cell. The 3DCoB cell has internally two inter-tier vias.
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3D Cell-on-Buffer (3DCoB)
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The advantage of the 3DCoB 3DCoB cells can be used by the conventional 2D place and route tools. No need for inter-tier routing metal layers between cells. Improve the overall performance by decreasing the input gate capacitance of the cells.
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Design Flow 3DCoB generation process
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Design Flow For example 2-input AND gate (AND2) with drive 42 (AND2x42) Minimum drive for all the 2-input AND gate is 4 (AND2x4) 3DCoB cell will be the min-drive AND2 cell (AND2x4) connected to the equivalent drive buffer (BUFx42)
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Design Flow
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Full design flow for 3DCoB approach
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Experimental Results
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Conclusions 3D monolithic integration technology offers a fine grain integration level thanks to high density and low-parasitics inter-tier vias. This paper introduced 3DCoB as a new design approach which is fully compatible with the conventional 2D implementation design flow tools.
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