Copyright  1997 RASSP E&F 1 VHDL Synthesis Module 60 RASSP Education & Facilitation Program M60_01_00 February 1998 Copyright  1998 RASSP E&F All rights.

Copyright  1997 RASSP E&F 1 VHDL Synthesis Module 60 RASSP Education & Facilitation Program M60_01_00 February 1998 Copyright  1998 RASSP E&F All rights reserved. This information is copyrighted by the RASSP E&F Program and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the RASSP E&F Program is prohibited. All information contained herein may be duplicated for non-commercial educational use provided this copyright notice is included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. FEEDBACK: The RASSP E&F Program welcomes and encourages any feedback that you may have including any changes that you may make to improve or update the material. You can contact us at feedback@rassp.scra.org or http://rassp.scra.org/module-request/FEEDBACK/feedback-on-modules.html

Copyright  1997 RASSP E&F 2 Rapid Prototyping Design Process VHDL Synthesis SYSTEM DEF. FUNCTION DESIGN H/W & S/W PART. H/W DESIGN S/W DESIGN H/W FAB H/W CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware H/W & S/W CO-DESIGN

Copyright  1997 RASSP E&F 3 Module Goals l Introduce and describe levels of synthesis m Algorithmic m RTL m Logic l Present VHDL syntax for synthesis m Combinational logic synthesis m Sequential logic synthesis m RTL level synthesis

Copyright  1997 RASSP E&F 4 Module Outline l Synthesis Background l VHDL Packages for Synthesis l VHDL for Combinational Logic Synthesis m Types m Attributes m Concurrent signal assignment statements m Operators m Processes m If statements m Case statements m Loops m Procedures and functions m Tri state logic m Use of don’t cares m After clauses m Inferring latches m Problems to avoid

Copyright  1997 RASSP E&F 5 Module Outline l VHDL for Sequential Logic Synthesis m Level sensitive sequential logic m Edge sensitive sequential logic m Finite state machines m Sequential datapaths l VHDL for RTL Level Synthesis l Structural VHDL l Implementation Technology Considerations l Summary

Copyright  1997 RASSP E&F 6 Module Outline l Synthesis Background l VHDL Packages for Synthesis l VHDL for Combinational Logic Synthesis l VHDL for Sequential Logic Synthesis l VHDL for RTL Level Synthesis l Structural VHDL l Implementation Technology Considerations l Summary

Copyright  1997 RASSP E&F 7 Hardware Synthesis l Hardware Synthesis is the process of mapping an input specification for a hardware design into a hardware implementation m The input specification contains the behavioral information - what functions the final implementations is to perform, m The input specification DOES NOT specify how the functions are to be performed [Parker84]

Copyright  1997 RASSP E&F 8 Definitions Abstract behavior The operation of a digital hardware module in terms of reads and writes of variables to and from the outside world, the conditions on the reads and writes, the values of the output variables, and their partial orderings Control-flow behavior The operation of a digital hardware module in terms of the loops, conditional branches, and ordering of functions performed by the module Data paths The hardware which stores and performs operations on data [Parker84]

Copyright  1997 RASSP E&F 9 Definitions (Cont.) Gate level The stage of hardware design at which the operations and storage elements can be described in terms of their constructions from logic gates such as NAND and OR Logic level Sometimes synonymous with gate level; often used when the hardware is described in terms of Boolean equations Register-transfer level The hardware implementation stage at which the hardware is described in terms of transfers of data between registers and operations on the data, which are usually expressed as bit vectors rather than as single-bit values; includes register-transfer behavior and register- transfer structure [Parker84]

Copyright  1997 RASSP E&F 1010 Definitions (Cont.) Register-transfer behavior The operation of hardware at the register-transfer level; only abstract or visible transfers and registers are described; interconnections between registers and functional units are usually implicit; control signals and overall control flow are usually implicit and/or expressed at a high level Register-transfer structure Hardware implementation at the register-transfer level; register, functional operators, and their interconnections are specified; the control signals and overall control flow may be embedded in the hardware as part of the overall specification or may be specified separately; sometimes referred to as the functional structure [Parker84]

Copyright  1997 RASSP E&F1 Synthesis Goals l Synthesis attempts to produce designs with: m Maximum speed m Minimum area m Minimum pin count m Minimum power consumption m Minimum design time m Maximum reliability m Maximum testability [Parker84]

Copyright  1997 RASSP E&F 1212 [Parker84] Synthesis Constraints l Synthesis may be subject to a series of constraints: m Limitations of a given implementation technology (i.e., no tri-state devices available, no built-in memory cells) m Specified time delays between significant events m Area upper bounds m Pin count upper bounds m Upper bound on tool execution time m Lower bound on reliability m Lower bound on test coverage (testability)

Copyright  1997 RASSP E&F 1313 [Parker84] Synthesis Processes l Synthesis is composed of the following processes: m Resource allocation - selection of structures to implement functions m Design transformation - changing a design to meet a goal of constraint without adding additional detail (optimization) m (De)composition - partitioning or combining functions so that they directly map to structures available in the target technology (technology mapping) m Event scheduling - assigning operations to clock phases or slots on a time axis

Copyright  1997 RASSP E&F 1414 Synthesis Categories l Algorithm Synthesis - (also called Behavioral Synthesis) - synthesis of abstract behavior or control-flow behavior from a high level algorithm description m Involves high-level scheduling and assignment l Register-Transfer Synthesis - synthesis of register-transfer structure from abstract, control- flow, or register-transfer behavior l Logic Synthesis - synthesis of gate-level logic (an implementation) from register-transfer structure or Boolean equations [Parker84]

Copyright  1997 RASSP E&F 1515 Behavioral Synthesis + * + * E(7:0)A(7:0)B(7:0) G(15:0)F(15:0) D(7:0)C(7:0) + * + * E(7:0)A(7:0)B(7:0) G(15:0)F(15:0) D(7:0)C(7:0) t1 t2 t3 [Parker84] f <= (a + b) * e; g <= (a + b) * (c + d); f <= (a + b) * e; g <= (a + b) * (c + d);

Copyright  1997 RASSP E&F 1616 Behavioral Synthesis (cont.) + * + * E(7:0)A(7:0)B(7:0) G(15:0)F(15:0) D(7:0)C(7:0) t1 t2 t3 Select B; Load R2; Select A; Load R1; Add; Load R4; Register R1 Register R2 Register R3 Register R4 + * Register R3 Register R4 E(7:0) A(7:0)B(7:0)D(7:0)C(7:0) G(15:0)F(15:0) Data Path BehaviorControl Flow (not all shown) [Parker84]

Copyright  1997 RASSP E&F 1717 RTL Level Synthesis Select B; Load R2; Select A; Load R1; Add; Load R4; Register R1 Register R2 Register R3 Register R4 + * Register R3 Register R4 E(7:0) A(7:0)B(7:0)D(7:0)C(7:0) G(15:0)F(15:0) Data Path BehaviorControl Flow (not all shown) R1 R2 A(7:0)B(7:0)D(7:0)C(7:0) ALU RTL Structure (not all shown) Select B; Load R2; Select A; Load R1; Add; Load R4; RTL Control Flow (not all shown) [Parker84]

Copyright  1997 RASSP E&F 1818 Logic Synthesis R1 R2 A(7:0)B(7:0)D(7:0)C(7:0) ALU RTL Structure (not all shown) Select B; Load R2; Select A; Load R1; Add; Load R4; RTL Control Flow (not all shown) [Parker84]

Copyright  1997 RASSP E&F 2020 VHDL Packages for Synthesis Base Types l Standard bit types may be used l Typically IEEE 1164 Std. types are used m std_ulogic type q Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); m std_logic type - resolved std_ulogic type USE IEEE.std_logic_1164.ALL;

Copyright  1997 RASSP E&F 2121 VHDL Packages for Synthesis Base Types (cont.) l The std_logic_1164 package also contains: m Vectors of std_ulogic and std_logic m Subtypes of std_logic - X01, X01Z, UX01, UX10Z m Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector FUNCTION “and” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xnor” (l,r : std_ulogic;) return ux01; FUNCTION "not" (l,r : std_ulogic) RETURN UX01; FUNCTION “and” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xnor” (l,r : std_ulogic;) return ux01; FUNCTION "not" (l,r : std_ulogic) RETURN UX01; m Conversion functions FUNCTION To_bit(s:std_ulogic) RETURN bit; FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic; FUNCTION To_bit(s:std_ulogic) RETURN bit; FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;

Copyright  1997 RASSP E&F2 VHDL Packages for Synthesis Base Types (cont.) m Unknown functions FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean; m Clock edge functions FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_ulogic) RETURN boolean; FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_ulogic) RETURN boolean;

Copyright  1997 RASSP E&F 2323 VHDL Packages for Synthesis Arithmetic Packages l All synthesis tools support some type of arithmetic packages l Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools m std_logic_arith m std_logic_signed m std_logic_unsigned l Actel synthesis tools support their own package m asyl.arith l IEEE has developed standard packages for synthesis IEEE Std. 1076.3 m Numeric_Bit m Numeric_Std

Copyright  1997 RASSP E&F 2424 IEEE Std 1076.3 Packages Numeric_Bit l Type declarations for signed and unsigned numbers TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit; TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit; l Arithmetic operators - various combinations of signed and unsigned arguments FUNCTION “abs” (arg:unsigned) RETURN unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION “+” (l,r:unsigned) RETURN unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION “*” (l,r:unsigned) RETURN unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION “rem” (l,r:unsigned) RETURN unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; FUNCTION “abs” (arg:unsigned) RETURN unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION “+” (l,r:unsigned) RETURN unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION “*” (l,r:unsigned) RETURN unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION “rem” (l,r:unsigned) RETURN unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; USE IEEE.numeric_bit.ALL;

Copyright  1997 RASSP E&F 2525 IEEE Std 1076.3 Packages Numeric_Bit l Comparison operators - various combinations of signed and unsigned arguments FUNCTION “>” (l,r:unsigned) RETURN boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION “<=” (l,r:unsigned) RETURN boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION “=” (l,r:unsigned) RETURN boolean; FUNCTION “/=” (l,r:unsigned) RETURN boolean; FUNCTION “>” (l,r:unsigned) RETURN boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION “<=” (l,r:unsigned) RETURN boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION “=” (l,r:unsigned) RETURN boolean; FUNCTION “/=” (l,r:unsigned) RETURN boolean; l Shift and rotate functions FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION sll (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rol (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION sll (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rol (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned;

Copyright  1997 RASSP E&F 2626 IEEE Std 1076.3 Packages Numeric_Bit l Resize functions FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; l Conversion functions FUNCTION to_integer (arg:unsigned) RETURN natural; FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; FUNCTION to_integer (arg:unsigned) RETURN natural; FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; l Logical operators FUNCTION “not” (l:unsigned) RETURN unsigned; FUNCTION “and” (l,r:unsigned) RETURN unsigned; FUNCTION “or” (l,r:unsigned) RETURN unsigned; FUNCTION “nand” (l,r:unsigned) RETURN unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION “xnor” (l,r:unsigned) RETURN unsigned; FUNCTION “not” (l:unsigned) RETURN unsigned; FUNCTION “and” (l,r:unsigned) RETURN unsigned; FUNCTION “or” (l,r:unsigned) RETURN unsigned; FUNCTION “nand” (l,r:unsigned) RETURN unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION “xnor” (l,r:unsigned) RETURN unsigned; l Edge detection functions FUNCTION rising_edge(SIGNAL s:bit) RETURN boolean; FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean; FUNCTION rising_edge(SIGNAL s:bit) RETURN boolean; FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean;

Copyright  1997 RASSP E&F 2727 IEEE Std 1076.3 Packages Numeric_Std l Similar to Numeric_Bit package using std_logic_1164 types m Signed and unsigned type declarations m Aritmetic operators m Comparison operators m Shift and rotate functions m Resize functions m Conversion functions m Logical operators m Match functions FUNCTION std_match (l,r:std_ulogic) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; FUNCTION std_match (l,r:std_ulogic) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; m Translation functions FUNCTION to_01 (s:unsigned; xmap:std_logic := ‘0’) RETURN unsigned; USE IEEE.numeric_std.ALL;

Copyright  1997 RASSP E&F 2828 Module Outline l Synthesis Background l VHDL Packages for Synthesis l VHDL for Combinational Logic Synthesis m Types m Attributes m Concurrent signal assignment statements m Operators m Processes m If statements m Case statements m Loops m Procedures and functions m Tri state logic m Use of don’t cares m After clauses m Inferring latches m Problems to avoid l VHDL for Sequential Logic Synthesis l VHDL for RTL Level Synthesis l Structural VHDL l Implementation Technology Considerations l Summary

Copyright  1997 RASSP E&F 2929 Types l Scalar types m Enumeration types are supported q Bit, Boolean, and Std_Ulogic map to single bits  Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used q Character type is suppored q Severity_level type is ignored m Integer type, Natural, and Positive are supported q A subtype with a descrete range should be used or the default 32 bit length will be synthesized m Physical types (e.g., time) are ignored  Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc.

Copyright  1997 RASSP E&F 3030 Types (cont.) l Array types are supported m Bounds must be specified directly or indirectly as static values of an integer type m Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits TYPE integer_array IS ARRAY(natural RANGE 7 DOWNTO 0) OF integer; TYPE boolean_array IS ARRAY(integer RANGE <>) OF boolean;... SIGNAL bool_sig : boolean_array(-1 to 1); TYPE integer_array IS ARRAY(natural RANGE 7 DOWNTO 0) OF integer; TYPE boolean_array IS ARRAY(integer RANGE <>) OF boolean;... SIGNAL bool_sig : boolean_array(-1 to 1); l Record types are supported l Access types are ignored l File types are ignored m File objects and file operations are not supported

Copyright  1997 RASSP E&F 3131 Attributes l The following predefined attributes for types are supported: m t’BASE m t’LEFT m t’RIGHT m t’HIGH m t’LOW l The following predefined attributes for array objects are supported: m a’LEFT m a’RIGHT m a’HIGH m a’LOW m a’RANGE m a’REVERSE_RANGE m a’LENGTH l The following predefined attributes for signals are supported m s’STABLE  s’EVENT User defined attributes other than ENUM_ENCODING are NOT supported

Copyright  1997 RASSP E&F 3232 Concurrent Signal Assignment Statements l Simple concurrent signal assignment statements are supported m Multiple waveform elements are not allowed library IEEE; use IEEE.std_logic_1164.all; ENTITY csa is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END csa; ARCHITECTURE behavior OF csa IS BEGIN y <= a NOR b; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY csa is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END csa; ARCHITECTURE behavior OF csa IS BEGIN y <= a NOR b; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_csa is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_csa; ARCHITECTURE behavior OF aoi_csa IS SIGNAL sig1,sig2 : std_logic; BEGIN sig1 <= a AND b; sig2 <= c OR sig1; y <= NOT sig2; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_csa is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_csa; ARCHITECTURE behavior OF aoi_csa IS SIGNAL sig1,sig2 : std_logic; BEGIN sig1 <= a AND b; sig2 <= c OR sig1; y <= NOT sig2; END behavior;

Copyright  1997 RASSP E&F3 Conditional Signal Assignment Statements Concurrent conditional signal assignment statements are supported - must end in else clause library IEEE; use IEEE.std_logic_1164.all; ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic); END mux2; ARCHITECTURE behavior OF mux2 IS BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic); END mux2; ARCHITECTURE behavior OF mux2 IS BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior;

Copyright  1997 RASSP E&F 3434 Selected Signal Assignment Statements l Concurrent selected signal assignment statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4; ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4; ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS; END behavior;

Copyright  1997 RASSP E&F 3535 Operators l Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported m Arithmetic operators - “abs”, “+”, “-”, “*”, “/”, “rem”, “mod” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY divider is PORT(divisor : IN unsigned(1 DOWNTO 0); dividend : IN unsigned(1 DOWNTO 0); quotient : OUT unsigned(1 DOWNTO 0)); END divider; ARCHITECTURE behavior OF divider IS BEGIN quotient <= dividend / divisor; END behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY divider is PORT(divisor : IN unsigned(1 DOWNTO 0); dividend : IN unsigned(1 DOWNTO 0); quotient : OUT unsigned(1 DOWNTO 0)); END divider; ARCHITECTURE behavior OF divider IS BEGIN quotient <= dividend / divisor; END behavior;

Copyright  1997 RASSP E&F 3636 Operators (cont.) l Comparison operators - “>”, “ =“, “=“, “/=“ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY compare is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(3 DOWNTO 0); aleb : OUT boolean); END compare; ARCHITECTURE behavior OF compare IS BEGIN aleb <= (a <= b); END behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY compare is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(3 DOWNTO 0); aleb : OUT boolean); END compare; ARCHITECTURE behavior OF compare IS BEGIN aleb <= (a <= b); END behavior;

Copyright  1997 RASSP E&F 3737 Operators (cont.) l Shift and conversion operators - “shift_left”, “shift_right”, “rotate_left”, “rotate_right”, “resize”, “to_integer”, “to_unsigned” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY shift_4 is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(1 DOWNTO 0); y : OUT unsigned(3 DOWNTO 0)); END shift_4; ARCHITECTURE behavior OF shift_4 IS BEGIN y <= shift_left(a,to_integer(b)); END behavior; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY shift_4 is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(1 DOWNTO 0); y : OUT unsigned(3 DOWNTO 0)); END shift_4; ARCHITECTURE behavior OF shift_4 IS BEGIN y <= shift_left(a,to_integer(b)); END behavior;

Copyright  1997 RASSP E&F 3838 Process Statements l Process statements are supported l Postponed processes (or postponed concurrent signal assignment statements) are NOT supported Process statement can have either a sensitivity list or a WAIT statement m Sensitivity list is ignored for synthesis (by most tools) - thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list  Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN  Only the WAIT UNTIL syntax of the WAIT statement is supported WAIT UNTIL input1 = ‘1’; WAIT UNTIL clock’EVENT and clock = ‘1’; WAIT UNTIL input1 = ‘1’; WAIT UNTIL clock’EVENT and clock = ‘1’;

Copyright  1997 RASSP E&F 3939 Process Statements Example library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c,sig1) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c,sig1) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F 4040 Process Statements Incomplete Sensitivity List library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; a y 0 5 10 15 20 b c sig1 0 U

Copyright  1997 RASSP E&F 4141 Sequential Signal Assignment Statements l Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported  IF statements  Case statements  Loop statement  Only For loops supported q Bounds must be specified as static values of an integer type  Exit and Next statements supported (without lables)

Copyright  1997 RASSP E&F 4242 Sequential IF Statements IF statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY xor_process is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END xor_process; ARCHITECTURE behavior OF xor_process IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= '0'; END IF; END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY xor_process is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END xor_process; ARCHITECTURE behavior OF xor_process IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= '0'; END IF; END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F 4343 Sequential Case Statements Case statements are supported m Choices which include metalogical values are never taken library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4_process; ARCHITECTURE behavior OF mux4_process IS BEGIN comb : PROCESS(a,b,c,d,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN "11" => y <= d; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4_process; ARCHITECTURE behavior OF mux4_process IS BEGIN comb : PROCESS(a,b,c,d,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN "11" => y <= d; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F4 Sequential Loop Statements Only For loops with integer range are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY shift4 is PORT(mode : IN std_logic; shift_in : IN std_logic; a : IN std_logic_vector(4 DOWNTO 1); y : OUT std_logic_vector(4 DOWNTO 1); shift_out : OUT std_logic); END shift4; library IEEE; use IEEE.std_logic_1164.all; ENTITY shift4 is PORT(mode : IN std_logic; shift_in : IN std_logic; a : IN std_logic_vector(4 DOWNTO 1); y : OUT std_logic_vector(4 DOWNTO 1); shift_out : OUT std_logic); END shift4; ARCHITECTURE behavior OF shift4 IS SIGNAL in_temp : std_logic_vector(5 DOWNTO 0); SIGNAL out_temp : std_logic_vector(5 DOWNTO 1); BEGIN in_temp(0) <= shift_in; in_temp(4 DOWNTO 1) <= a; in_temp(5) <= '0'; comb : PROCESS(mode,in_temp,a) BEGIN FOR i IN 1 TO 5 LOOP IF(mode = '0') THEN out_temp(i) <= in_temp(i-1); ELSE out_temp(i) <= in_temp(i); END IF; END LOOP; END PROCESS comb; y <= out_temp(4 DOWNTO 1); shift_out <= out_temp(5); END behavior; ARCHITECTURE behavior OF shift4 IS SIGNAL in_temp : std_logic_vector(5 DOWNTO 0); SIGNAL out_temp : std_logic_vector(5 DOWNTO 1); BEGIN in_temp(0) <= shift_in; in_temp(4 DOWNTO 1) <= a; in_temp(5) <= '0'; comb : PROCESS(mode,in_temp,a) BEGIN FOR i IN 1 TO 5 LOOP IF(mode = '0') THEN out_temp(i) <= in_temp(i-1); ELSE out_temp(i) <= in_temp(i); END IF; END LOOP; END PROCESS comb; y <= out_temp(4 DOWNTO 1); shift_out <= out_temp(5); END behavior;

Copyright  1997 RASSP E&F 4545 Procedures and Functions l Procedures and Functions are supported - with limitations to allowed statement types m Procedures and functions may be in a package or in the declarative part of the architecture LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; PACKAGE logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic; PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)); END logic_package; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; PACKAGE logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic; PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)); END logic_package;

Copyright  1997 RASSP E&F 4646 Procedures and Functions (cont.) PACKAGE BODY logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic IS VARIABLE result : std_logic; BEGIN IF((in1 = '1' and in2 = '1') or (in2 = '1' and in3 = '1') or (in1 = '1' and in3 = '1')) THEN result := '1'; ELSIF((in1 = '0' and in2 = '0') or (in2 = '0' and in3 = '0') or (in1 = '0' and in3 = '0')) THEN result := '0'; ELSE result := 'X'; END IF; RETURN result; END majority; PACKAGE BODY logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic IS VARIABLE result : std_logic; BEGIN IF((in1 = '1' and in2 = '1') or (in2 = '1' and in3 = '1') or (in1 = '1' and in3 = '1')) THEN result := '1'; ELSIF((in1 = '0' and in2 = '0') or (in2 = '0' and in3 = '0') or (in1 = '0' and in3 = '0')) THEN result := '0'; ELSE result := 'X'; END IF; RETURN result; END majority;

Copyright  1997 RASSP E&F 4747 Procedures and Functions (cont.) PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) IS BEGIN CASE input IS WHEN "00" => output <= "0001"; WHEN "01" => output <= "0010"; WHEN "10" => output <= "0100"; WHEN "11" => output <= "1000"; WHEN OTHERS => output <= "XXXX"; END CASE; END decode; END logic_package; PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) IS BEGIN CASE input IS WHEN "00" => output <= "0001"; WHEN "01" => output <= "0010"; WHEN "10" => output <= "0100"; WHEN "11" => output <= "1000"; WHEN OTHERS => output <= "XXXX"; END CASE; END decode; END logic_package;

Copyright  1997 RASSP E&F 4848 Using Procedures and Functions LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY voter IS PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END voter; ARCHITECTURE maj OF voter IS BEGIN y <= majority(a,b,c); END maj; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY voter IS PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END voter; ARCHITECTURE maj OF voter IS BEGIN y <= majority(a,b,c); END maj;

Copyright  1997 RASSP E&F 4949 Using Procedures and Functions (cont.) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY decoder IS PORT(y : IN std_logic_vector(1 DOWNTO 0); g : OUT std_logic_vector(3 DOWNTO 0)); END decoder; ARCHITECTURE dec OF decoder IS BEGIN comb : PROCESS(y) BEGIN decode(y,g); END PROCESS comb; END dec; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY decoder IS PORT(y : IN std_logic_vector(1 DOWNTO 0); g : OUT std_logic_vector(3 DOWNTO 0)); END decoder; ARCHITECTURE dec OF decoder IS BEGIN comb : PROCESS(y) BEGIN decode(y,g); END PROCESS comb; END dec;

Copyright  1997 RASSP E&F 5050 Tri-State Logic l Tri-state logic is infered when an object is assigned an IEEE Std. 1164 value ‘Z’ library IEEE; use IEEE.std_logic_1164.all; ENTITY tri_state4 is PORT(enable : IN std_logic; a : IN std_logic_vector(3 DOWNTO 0); y : OUT std_logic_vector(3 DOWNTO 0)); END tri_state4; ARCHITECTURE behavior OF tri_state4 IS BEGIN y <= a WHEN (enable = '1') ELSE "ZZZZ"; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY tri_state4 is PORT(enable : IN std_logic; a : IN std_logic_vector(3 DOWNTO 0); y : OUT std_logic_vector(3 DOWNTO 0)); END tri_state4; ARCHITECTURE behavior OF tri_state4 IS BEGIN y <= a WHEN (enable = '1') ELSE "ZZZZ"; END behavior;

Copyright  1997 RASSP E&F 5151 Use of Don’t Cares (‘X’s) l IEEE Std. 1164 values of ‘X’ or ‘-’ can be used to specify “don’t care” conditions library IEEE; use IEEE.std_logic_1164.all; ENTITY not_xor is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END not_xor; ARCHITECTURE behavior OF not_xor IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= 'X'; -- could also be ‘-’ END IF; END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY not_xor is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END not_xor; ARCHITECTURE behavior OF not_xor IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= 'X'; -- could also be ‘-’ END IF; END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F 5252 After Clauses l Although not defined by the language, most simulator’s waveform windows do not show VHDL delta cycles adequately, if at all l Debugging large behavioral simulations before synthesis can be difficult if no delays are used - everything appears to happen simultaneously l List windows typically show delta cycles, but can be difficult to interpret The solution is to put “dummy” delays in the behavioral descriptions using After clauses to “spread out” the events After clauses are ignored for synhtesis CONSTANT delay : TIME := 5 ns;... output <= input + 1 AFTER delay; CONSTANT delay : TIME := 5 ns;... output <= input + 1 AFTER delay;

Copyright  1997 RASSP E&F 5353 Inferring Latches If signals or variables are not assigned values in some conditional expressions of IF or Case statements, level-sensitive sequential logic might result library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3_seq is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3_seq; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3_seq is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3_seq; ARCHITECTURE behavior OF mux3_seq IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => --empty END CASE; END PROCESS comb; END behavior; ARCHITECTURE behavior OF mux3_seq IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => --empty END CASE; END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F 5454 Avioding Latches l Assigning values of “don’t care” (‘X’ or ‘-’) in these cases can avoid this library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3; ARCHITECTURE behavior OF mux3 IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY mux3 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux3; ARCHITECTURE behavior OF mux3 IS BEGIN comb : PROCESS(a,b,c,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior;

Copyright  1997 RASSP E&F5 Problems to Avoid Inferring Latches in Complex Behaviors ARCHITECTURE rtl OF pc_comb IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(dat_in, cntrl, pc) BEGIN CASE cntrl IS WHEN "01" => pc <= (pc + "0001"); WHEN "10" => pc <= pc; WHEN OTHERS => pc <= data_in; END CASE; END PROCESS one; DATA_OUT <= PC; END rtl; ARCHITECTURE rtl OF pc_comb IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(dat_in, cntrl, pc) BEGIN CASE cntrl IS WHEN "01" => pc <= (pc + "0001"); WHEN "10" => pc <= pc; WHEN OTHERS => pc <= data_in; END CASE; END PROCESS one; DATA_OUT <= PC; END rtl; library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; ENTITY pc_comb IS PORT(data_in : IN unsigned(3 DOWNTO 0); cntrl : IN unsigned(1 DOWNTO 0); data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb; library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.numeric_std.ALL; ENTITY pc_comb IS PORT(data_in : IN unsigned(3 DOWNTO 0); cntrl : IN unsigned(1 DOWNTO 0); data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb;

Copyright  1997 RASSP E&F 5656 Problems to Avoid Synthesizing Asynchronous State Machines! library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY pc_comb2 is PORT(dat_in : IN unsigned(3 DOWNTO 0); cntrl : IN std_logic; data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb2; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY pc_comb2 is PORT(dat_in : IN unsigned(3 DOWNTO 0); cntrl : IN std_logic; data_out : OUT unsigned(3 DOWNTO 0)); END pc_comb2; ARCHITECTURE rtl OF pc_comb2 IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(data_in, cntrl, pc) BEGIN CASE cntrl IS WHEN '1' => pc <= (pc + "0001"); WHEN '0' => pc <= data_in; WHEN OTHERS => pc <= "XXXX"; END CASE; END PROCESS one; dat_out <= pc; END rtl; ARCHITECTURE rtl OF pc_comb2 IS SIGNAL pc : unsigned(3 DOWNTO 0); BEGIN one : PROCESS(data_in, cntrl, pc) BEGIN CASE cntrl IS WHEN '1' => pc <= (pc + "0001"); WHEN '0' => pc <= data_in; WHEN OTHERS => pc <= "XXXX"; END CASE; END PROCESS one; dat_out <= pc; END rtl;

Copyright  1997 RASSP E&F 5757 Module Outline l Synthesis Background l VHDL Packages for Synthesis l VHDL for Combinational Logic Synthesis l VHDL for Sequential Logic Synthesis m Level sensitive sequential logic m Edge sensitive sequential logic m Finite state machines m Sequential datapaths l VHDL for RTL Level Synthesis l Structural VHDL l Implementation Technology Considerations l Summary

Copyright  1997 RASSP E&F 5858 Level Sensitive D Latch Use IF statement without Else clause library IEEE; use IEEE.std_logic_1164.all; ENTITY d_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_latch; ARCHITECTURE behavior OF d_latch IS BEGIN seq : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY d_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_latch; ARCHITECTURE behavior OF d_latch IS BEGIN seq : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior;

Copyright  1997 RASSP E&F 5959 Master-Slave D Latch (D Flip-Flop) library IEEE; use IEEE.std_logic_1164.all; ENTITY ms_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END ms_latch; ARCHITECTURE behavior OF ms_latch IS SIGNAL q_int : std_logic; BEGIN seq1 : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q_int <= d; END IF; END PROCESS seq1; seq2 : PROCESS(q_int,clk) BEGIN IF(clk = '0') THEN q <= q_int; END IF; END PROCESS seq2; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY ms_latch is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END ms_latch; ARCHITECTURE behavior OF ms_latch IS SIGNAL q_int : std_logic; BEGIN seq1 : PROCESS(d,clk) BEGIN IF(clk = '1') THEN q_int <= d; END IF; END PROCESS seq1; seq2 : PROCESS(q_int,clk) BEGIN IF(clk = '0') THEN q <= q_int; END IF; END PROCESS seq2; qn <= not q; END behavior; Optimize

Copyright  1997 RASSP E&F 6060 Edge Sensitive D Flip-Flop library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff; ARCHITECTURE behavior OF d_ff IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff; ARCHITECTURE behavior OF d_ff IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; l Clocks must be of BIT or STD_LOGIC type - metalogic values not allowed l Rising_edge() and Falling_edge() functions can be used to specify clock edge

Copyright  1997 RASSP E&F 6161 Edge Sensitive D Flip-Flop (cont.) library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_w is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_w; ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL rising_edge(clk); q <= d; END PROCESS seq; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_w is PORT(d : IN std_logic; clk : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_w; ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL rising_edge(clk); q <= d; END PROCESS seq; qn <= not q; END behavior; l Wait statement can be used ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL clk = ‘1’; q <= d; END PROCESS seq; qn <= not q; END behavior; ARCHITECTURE behavior OF d_ff_w IS BEGIN seq : PROCESS BEGIN WAIT UNTIL clk = ‘1’; q <= d; END PROCESS seq; qn <= not q; END behavior;

Copyright  1997 RASSP E&F 6262 Edge Sensitive Flip-Flops library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_pc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_pc; ARCHITECTURE behavior OF d_ff_pc IS BEGIN seq : PROCESS(clk,pre,clr) BEGIN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSIF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_pc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_pc; ARCHITECTURE behavior OF d_ff_pc IS BEGIN seq : PROCESS(clk,pre,clr) BEGIN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSIF(rising_edge(clk)) THEN q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; l Preset and clear functions can be added m Asynchronous with respect to the clock

Copyright  1997 RASSP E&F 6363 Edge Sensitive Flip-Flops library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_spc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_spc; ARCHITECTURE behavior OF d_ff_spc IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSE q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY d_ff_spc is PORT(d : IN std_logic; clk : IN std_logic; pre : IN std_logic; clr : IN std_logic; q : INOUT std_logic; qn : OUT std_logic); END d_ff_spc; ARCHITECTURE behavior OF d_ff_spc IS BEGIN seq : PROCESS(clk) BEGIN IF(rising_edge(clk)) THEN IF(pre = '0') THEN q <= '1'; ELSIF(clr = '0') THEN q <= '0'; ELSE q <= d; END IF; END PROCESS seq; qn <= not q; END behavior; l Preset and clear functions can be added m Synchronous with respect to the clock

Copyright  1997 RASSP E&F 6464 Finite State Machine Synthesis l State machines can be modeled as a combinational portion and a sequential portion l Both Mealy and Moore type state machines can be described l Most synthesis tools employ special algorithms to minimize state machines - thus standard procedures must be used to enable the tool to recognize the state machine Combinational Logic Memory Present State Next State Primary Inputs Primary Outputs Huffman FSM Model

Copyright  1997 RASSP E&F 6565 Mealy and Moore State Machine Models Output Combinational Logic Memory Present State Next State Primary Inputs Primary Outputs Mealy Machine Model l A state machine has three basic parts m Next State Logic m Output Logic m Memory l The most straight-forward way to code a synthesizable state machine is to use one process per function Next State Combinational Logic Output Combinational Logic Memory Present State Next State Primary Inputs Primary Outputs Moore Machine Model Next State Combinational Logic

Copyright  1997 RASSP E&F6 State Machine State Encoding l Use enumerated type to encode state variables TYPE state_type IS (idle,init,test,add,shift); SIGNAL present_state, next_state : state_type; TYPE state_type IS (idle,init,test,add,shift); SIGNAL present_state, next_state : state_type; l User can choose state encoding type in synthesis tool m Sequential m One Hot m Gray m Transition Optimized m Others enum_encoding attribute can be used to specify encoding directly ATTRIBUTE enum_encoding:STRING; TYPE state_type IS (idle,init,test,add,shift); ATTRIBUTE enum_encoding OF state_type:TYPE IS “000 100 110 001 011”; ATTRIBUTE enum_encoding:STRING; TYPE state_type IS (idle,init,test,add,shift); ATTRIBUTE enum_encoding OF state_type:TYPE IS “000 100 110 001 011”;

Copyright  1997 RASSP E&F 6767 State Machine Simple Example State Diagram Initialize Test Add Shift Idle START=‘1’ Q 0 =‘0’ Q 0 =‘1’

Copyright  1997 RASSP E&F 6868 State Machine Memory Process l Use flip-flop type process with asynchronous or synchronous reset m State machine MUST have reset to function correctly l Rising or falling edge may be used clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; END IF; END PROCESS clocked; clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; END IF; END PROCESS clocked;

Copyright  1997 RASSP E&F 6969 State Machine Next State Process l Next state process forms the heart of the state machine l Process is sensitive to present state and any necessary inputs Most tools prefer a Case statement syntax on which to run their state machine minimization algorithms nextstate : PROCESS(present_state,start,q0) BEGIN CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(q0='1') THEN next_state <= add; ELSIF(q0='0') THEN next_state <= shift; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; END CASE; END PROCESS nextstate; nextstate : PROCESS(present_state,start,q0) BEGIN CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(q0='1') THEN next_state <= add; ELSIF(q0='0') THEN next_state <= shift; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; END CASE; END PROCESS nextstate;

Copyright  1997 RASSP E&F 7070 State Machine Output Process l Output process computes output values based on the present state and the inputs (Mealy machine) on just on the present state (Moore machine) IF or Case statement may be used output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output;

Copyright  1997 RASSP E&F 7171 State Machine Putting it all together LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit; LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit; ARCHITECTURE fsm OF control_unit IS CONSTANT delay : time := 5 ns ; TYPE state_type IS ( idle, init, test, add, shift); SIGNAL present_state, next_state : state_type ; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; END IF; END PROCESS clocked; ARCHITECTURE fsm OF control_unit IS CONSTANT delay : time := 5 ns ; TYPE state_type IS ( idle, init, test, add, shift); SIGNAL present_state, next_state : state_type ; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; END IF; END PROCESS clocked; l Entity l Architecture declarative part l Memory process

Copyright  1997 RASSP E&F 7272 State Machine Putting it all together (cont.) output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; nextstate : PROCESS(present_state,start,q0) BEGIN CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(q0='1') THEN next_state <= add; ELSIF(q0='0') THEN next_state <= shift; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; END CASE; END PROCESS nextstate; nextstate : PROCESS(present_state,start,q0) BEGIN CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(q0='1') THEN next_state <= add; ELSIF(q0='0') THEN next_state <= shift; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; END CASE; END PROCESS nextstate; l Next state process l Output process

Copyright  1997 RASSP E&F 7373 State Machine Results

Copyright  1997 RASSP E&F 7474 State Machines Variations l It is possible to have additional state variables in a synthesizable FSM m E.g., a counter to count the number of cycles through a certain state l It is also possible to have more than one state machine in a given architecture m Separate enumerated state variables m Separate or combined state transition, clock and output processes

Copyright  1997 RASSP E&F 7575 State Machines Additional State Variables l Integer counter to count number of cycles through states LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit2 IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit2; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit2 IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit2; ARCHITECTURE fsm OF control_unit2 IS CONSTANT delay : time := 5 ns ; TYPE state_type IS (idle,init,test,add,shift); SUBTYPE count_type IS integer RANGE 15 DOWNTO 0; SIGNAL present_state, next_state : state_type ; SIGNAL present_count,next_count : count_type; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; present_count <= 0; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; END IF; END PROCESS clocked; ARCHITECTURE fsm OF control_unit2 IS CONSTANT delay : time := 5 ns ; TYPE state_type IS (idle,init,test,add,shift); SUBTYPE count_type IS integer RANGE 15 DOWNTO 0; SIGNAL present_state, next_state : state_type ; SIGNAL present_count,next_count : count_type; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; present_count <= 0; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; END IF; END PROCESS clocked; l Entity l Architecture declarative part l Memory process

Copyright  1997 RASSP E&F 7676 State Machines Additional State Variables nextstate : PROCESS(present_state,present_count,start,q0) BEGIN next_count <= present_count; CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(present_count<8 AND q0='1') THEN next_state <= add; ELSIF(present_count<8 AND q0='0') THEN next_state <= shift; ELSIF(present_count=7) THEN next_state <= idle; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; next_count <= present_count + 1; END CASE; END PROCESS nextstate; nextstate : PROCESS(present_state,present_count,start,q0) BEGIN next_count <= present_count; CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(present_count<8 AND q0='1') THEN next_state <= add; ELSIF(present_count<8 AND q0='0') THEN next_state <= shift; ELSIF(present_count=7) THEN next_state <= idle; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; next_count <= present_count + 1; END CASE; END PROCESS nextstate; l Next state process

Copyright  1997 RASSP E&F7 State Machines Additional State Variables output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; l Output process

Copyright  1997 RASSP E&F 7878 State Machines Additional State Variables - Results

Copyright  1997 RASSP E&F 7979 State Machines Combined State Machines l Two enumerated types for state variables m Entity m Architecture declarative part m Memory process LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit3 IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; hold : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit3; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY control_unit3 IS PORT(clk : IN std_logic; q0 : IN std_logic; reset : IN std_logic; start : IN std_logic; hold : IN std_logic; a_enable : OUT std_logic; a_mode : OUT std_logic; c_enable : OUT std_logic; m_enable : OUT std_logic); END control_unit3; ARCHITECTURE fsm OF control_unit3 IS CONSTANT delay : time := 5 ns ; TYPE state_type IS (idle,init,test,add,shift); TYPE status_type IS (done,go,stop); SUBTYPE count_type IS integer RANGE 15 DOWNTO 0; SIGNAL present_state, next_state : state_type ; SIGNAL present_count,next_count : count_type; SIGNAL present_status,next_status : status_type; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; present_count <= 0; present_status <= go; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; present_status <= next_status; END IF; END PROCESS clocked; ARCHITECTURE fsm OF control_unit3 IS CONSTANT delay : time := 5 ns ; TYPE state_type IS (idle,init,test,add,shift); TYPE status_type IS (done,go,stop); SUBTYPE count_type IS integer RANGE 15 DOWNTO 0; SIGNAL present_state, next_state : state_type ; SIGNAL present_count,next_count : count_type; SIGNAL present_status,next_status : status_type; BEGIN clocked : PROCESS(clk, reset) BEGIN IF (reset = '0') THEN present_state <= idle; present_count <= 0; present_status <= go; ELSIF (clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; present_status <= next_status; END IF; END PROCESS clocked;

Copyright  1997 RASSP E&F 8080 State Machines Combined State Machines CASE present_status IS WHEN go => IF(hold = '1') THEN next_status <= stop; ELSIF(present_count = 7) THEN next_status <= done; ELSE next_status <= go; END IF; WHEN stop => IF(hold = '1') THEN next_status <= stop; ELSE next_status <= go; END IF; WHEN done => next_status <= done; END CASE; END PROCESS nextstate; CASE present_status IS WHEN go => IF(hold = '1') THEN next_status <= stop; ELSIF(present_count = 7) THEN next_status <= done; ELSE next_status <= go; END IF; WHEN stop => IF(hold = '1') THEN next_status <= stop; ELSE next_status <= go; END IF; WHEN done => next_status <= done; END CASE; END PROCESS nextstate; l Next state process nextstate : PROCESS(present_state,present_count, present_status,hold,start,q0) BEGIN next_count <= present_count; CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(present_status = go AND q0='1') THEN next_state <= add; ELSIF(present_status = go AND q0='0') THEN next_state <= shift; ELSIF(present_status=done) THEN next_state <= idle; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; IF(present_status = go) THEN next_count <= present_count + 1; END IF; END CASE; nextstate : PROCESS(present_state,present_count, present_status,hold,start,q0) BEGIN next_count <= present_count; CASE present_state IS WHEN idle => IF(start='1') THEN next_state <= init; ELSE next_state <= idle; END IF; WHEN init => next_state <= test; WHEN test => IF(present_status = go AND q0='1') THEN next_state <= add; ELSIF(present_status = go AND q0='0') THEN next_state <= shift; ELSIF(present_status=done) THEN next_state <= idle; ELSE next_state <= test; END IF; WHEN add => next_state <= shift; WHEN shift => next_state <= test; IF(present_status = go) THEN next_count <= present_count + 1; END IF; END CASE;

Copyright  1997 RASSP E&F 8181 State Machines Combined State Machines output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; output : PROCESS(present_state,start,q0) BEGIN -- Default Assignment a_enable <= '0' after delay; a_mode <= '0' after delay; c_enable <= '0' after delay; m_enable <= '0' after delay; -- State Actions CASE present_state IS WHEN init => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN add => a_enable <= '1' after delay; c_enable <= '1' after delay; m_enable <= '1' after delay; WHEN shift => a_enable <= '1' after delay; a_mode <= '1' after delay; m_enable <= '1' after delay; WHEN OTHERS => NULL; END CASE; END PROCESS output; END fsm; l Output process

Copyright  1997 RASSP E&F 8282 State Machines Combined State Machines - Results

Copyright  1997 RASSP E&F 8383 Sequential Datapaths l Behavioral descriptions that describe datapaths and control units can be synthesized l Individual VHDL processes are used to describe combinational logic blocks, registers, and state machines l Layout of the datapath is “implied” by the interconnection of the processes via signals

Copyright  1997 RASSP E&F 8484 Sequential Datapaths Example - 8 Bit Multiplier l Unsigned 8 bit multiplier - uses simple algorithm l Datapath includes N bit register, N bit adder and 2N + 1 shift register l Separate processes are used to model the M, A, Q, and C registers, the adder, and the output, memory, and next state portions of the control unit Control Unit Multiplicand M n-1 M0M0 A n-1 A0A0 Multiplier Q n-1 Q0Q0 C n-Bit Adder Product Data Path

Copyright  1997 RASSP E&F 8585 Flow Chart for Unsigned 8 Bit Multiplier Controller START C, A  0 M  Multiplicand Q  Multiplier Count  0 Q 0 = 1? C, A  A + M Shift C,A,Q Count  Count + 1 NoYes Count = n ? NoYes END

Copyright  1997 RASSP E&F 8686 State Diagram for Unsigned 8 Bit Multiplier Controller Initialize Test Add Shift Idle START=‘1’ COUNT< n && Q 0 =‘0’COUNT< n && Q 0 =‘1’ COUNT= n Count= Count+1 Count=0

Copyright  1997 RASSP E&F 8787 Sequential Datapaths Example - 8 Bit Multiplier l Entity LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY multiplier8 IS PORT(start : IN std_logic; -- input to indicate start start_ack : OUT std_logic; -- output to acknowledge data clk : IN std_logic; reset : IN std_logic; a_input : IN unsigned(7 downto 0); b_input : IN unsigned(7 downto 0); product : OUT unsigned(15 DOWNTO 0); data : OUT std_logic; -- data present on outputs data_ack : IN std_logic); -- data acknowledgement END multiplier8; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY multiplier8 IS PORT(start : IN std_logic; -- input to indicate start start_ack : OUT std_logic; -- output to acknowledge data clk : IN std_logic; reset : IN std_logic; a_input : IN unsigned(7 downto 0); b_input : IN unsigned(7 downto 0); product : OUT unsigned(15 DOWNTO 0); data : OUT std_logic; -- data present on outputs data_ack : IN std_logic); -- data acknowledgement END multiplier8;

Copyright  1997 RASSP E&F8 Sequential Datapaths Example - 8 Bit Multiplier l Architecture declarative part l Concurrent signal assignment statements ARCHITECTURE synthesizable_behavior OF multiplier8 IS SUBTYPE count_integer IS integer RANGE 0 to 8; TYPE states IS (idle,initialize,test,shift,add,stop); SIGNAL present_state : states := idle; SIGNAL next_state : states := idle; SIGNAL present_count : count_integer; SIGNAL next_count : count_integer; SIGNAL a_enable : std_logic; SIGNAL a_reset : std_logic; SIGNAL a_mode : std_logic; SIGNAL c_enable : std_logic; SIGNAL c_reset : std_logic; SIGNAL m_enable : std_logic; SIGNAL q_enable : std_logic; SIGNAL q_mode : std_logic; SIGNAL e_enable : std_logic; SIGNAL c : std_logic; SIGNAL c_out : std_logic; SIGNAL multiplier : unsigned(7 DOWNTO 0); SIGNAL multiplicand : unsigned(7 DOWNTO 0); SIGNAL accumulator : unsigned(7 DOWNTO 0); SIGNAL adder_result : unsigned(7 DOWNTO 0); BEGIN product(15 DOWNTO 8) <= accumulator; product(7 DOWNTO 0) <= multiplier; ARCHITECTURE synthesizable_behavior OF multiplier8 IS SUBTYPE count_integer IS integer RANGE 0 to 8; TYPE states IS (idle,initialize,test,shift,add,stop); SIGNAL present_state : states := idle; SIGNAL next_state : states := idle; SIGNAL present_count : count_integer; SIGNAL next_count : count_integer; SIGNAL a_enable : std_logic; SIGNAL a_reset : std_logic; SIGNAL a_mode : std_logic; SIGNAL c_enable : std_logic; SIGNAL c_reset : std_logic; SIGNAL m_enable : std_logic; SIGNAL q_enable : std_logic; SIGNAL q_mode : std_logic; SIGNAL e_enable : std_logic; SIGNAL c : std_logic; SIGNAL c_out : std_logic; SIGNAL multiplier : unsigned(7 DOWNTO 0); SIGNAL multiplicand : unsigned(7 DOWNTO 0); SIGNAL accumulator : unsigned(7 DOWNTO 0); SIGNAL adder_result : unsigned(7 DOWNTO 0); BEGIN product(15 DOWNTO 8) <= accumulator; product(7 DOWNTO 0) <= multiplier;

Copyright  1997 RASSP E&F 8989 Sequential Datapaths Example - 8 Bit Multiplier l Multiplicand (M) register process l Multiplier (Q) shift register process m_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(m_enable = '1') THEN multiplicand(7 DOWNTO 0) <= a_input; END IF; END PROCESS m_reg; q_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(q_enable = '1') THEN IF(q_mode = '1') THEN multiplier(7 DOWNTO 0) <= b_input; ELSIF(q_mode = '0') THEN multiplier(6 DOWNTO 0) <= multiplier(7 DOWNTO 1); multiplier(7) <= accumulator(0); END IF; END PROCESS q_reg; m_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(m_enable = '1') THEN multiplicand(7 DOWNTO 0) <= a_input; END IF; END PROCESS m_reg; q_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(q_enable = '1') THEN IF(q_mode = '1') THEN multiplier(7 DOWNTO 0) <= b_input; ELSIF(q_mode = '0') THEN multiplier(6 DOWNTO 0) <= multiplier(7 DOWNTO 1); multiplier(7) <= accumulator(0); END IF; END PROCESS q_reg;

Copyright  1997 RASSP E&F 9090 Sequential Datapaths Example - 8 Bit Multiplier l Accumulator (A) shift register process l Carry (C) register process a_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(a_reset = '0') THEN accumulator <= "00000000"; ELSIF(a_enable = '1') THEN IF(a_mode = '1') THEN accumulator <= adder_result; ELSIF(q_mode = '0') THEN accumulator(6 DOWNTO 0) <= accumulator(7 DOWNTO 1); accumulator(7) <= c_out; END IF; END PROCESS a_reg; c_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(c_reset = '0') THEN c_out <= '0'; ELSIF(c_enable = '1') THEN c_out <= c; END IF; END PROCESS c_reg; a_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(a_reset = '0') THEN accumulator <= "00000000"; ELSIF(a_enable = '1') THEN IF(a_mode = '1') THEN accumulator <= adder_result; ELSIF(q_mode = '0') THEN accumulator(6 DOWNTO 0) <= accumulator(7 DOWNTO 1); accumulator(7) <= c_out; END IF; END PROCESS a_reg; c_reg : PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN IF(c_reset = '0') THEN c_out <= '0'; ELSIF(c_enable = '1') THEN c_out <= c; END IF; END PROCESS c_reg;

Copyright  1997 RASSP E&F 9191 Sequential Datapaths Example - 8 Bit Multiplier l Adder combinational logic block adder : PROCESS (multiplicand,accumulator) VARIABLE a_temp : unsigned(8 downto 0); VARIABLE b_temp : unsigned(8 downto 0); VARIABLE result : unsigned(8 downto 0); BEGIN a_temp(7 downto 0) := multiplicand; a_temp(8) := '0'; b_temp(7 downto 0) := accumulator; b_temp(8) := '0'; result := a_temp + b_temp; c <= result(8); adder_result <= result(7 downto 0); END PROCESS adder; adder : PROCESS (multiplicand,accumulator) VARIABLE a_temp : unsigned(8 downto 0); VARIABLE b_temp : unsigned(8 downto 0); VARIABLE result : unsigned(8 downto 0); BEGIN a_temp(7 downto 0) := multiplicand; a_temp(8) := '0'; b_temp(7 downto 0) := accumulator; b_temp(8) := '0'; result := a_temp + b_temp; c <= result(8); adder_result <= result(7 downto 0); END PROCESS adder;

Copyright  1997 RASSP E&F 9292 Sequential Datapaths Example - 8 Bit Multiplier l Control unit memory process l Control unit next state process controller_state_reg : PROCESS(clk,reset) BEGIN IF(reset = '1') THEN present_state <= idle; present_count <= 0; ELSIF(clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; END IF; END PROCESS controller_state_reg; controller_state_reg : PROCESS(clk,reset) BEGIN IF(reset = '1') THEN present_state <= idle; present_count <= 0; ELSIF(clk'EVENT AND clk = '1') THEN present_state <= next_state; present_count <= next_count; END IF; END PROCESS controller_state_reg; WHEN test => IF(present_count < 8) THEN IF(multiplier(0) = '0') THEN next_state <= shift; ELSE next_state <= add; END IF; ELSE next_state <= stop; END IF; next_count <= present_count; WHEN add => next_state <= shift; next_count <= present_count; WHEN shift => next_state <= test; next_count <= present_count+1; WHEN stop => IF(data_ack = '1') THEN next_state <= idle; ELSE next_state <= stop; END IF; WHEN OTHERS => next_state <= idle; next_count <= present_count; END CASE; END PROCESS controller_state_trans; WHEN test => IF(present_count < 8) THEN IF(multiplier(0) = '0') THEN next_state <= shift; ELSE next_state <= add; END IF; ELSE next_state <= stop; END IF; next_count <= present_count; WHEN add => next_state <= shift; next_count <= present_count; WHEN shift => next_state <= test; next_count <= present_count+1; WHEN stop => IF(data_ack = '1') THEN next_state <= idle; ELSE next_state <= stop; END IF; WHEN OTHERS => next_state <= idle; next_count <= present_count; END CASE; END PROCESS controller_state_trans; controller_state_trans : PROCESS(present_state, present_count,start,multiplier(0),data_ack) BEGIN next_state <= present_state; -- default case next_count <= present_count; -- default case CASE present_state IS WHEN idle => IF(start = '1') THEN next_state <= initialize; ELSE next_state <= idle; END IF; next_count <= 0; WHEN initialize => next_state <= test; next_count <= present_count; controller_state_trans : PROCESS(present_state, present_count,start,multiplier(0),data_ack) BEGIN next_state <= present_state; -- default case next_count <= present_count; -- default case CASE present_state IS WHEN idle => IF(start = '1') THEN next_state <= initialize; ELSE next_state <= idle; END IF; next_count <= 0; WHEN initialize => next_state <= test; next_count <= present_count;

Copyright  1997 RASSP E&F 9393 Sequential Datapaths Example - 8 Bit Multiplier l Control unit output process controller_output : PROCESS(present_state) BEGIN CASE present_state IS WHEN idle => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN initialize => a_enable <= '1'; a_reset <= '0'; a_mode <= '1'; c_enable <= '0'; c_reset <= '0'; m_enable <= '1'; q_enable <= '1'; q_mode <= '1'; e_enable <= '1'; start_ack <= '1'; data <= '0'; controller_output : PROCESS(present_state) BEGIN CASE present_state IS WHEN idle => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN initialize => a_enable <= '1'; a_reset <= '0'; a_mode <= '1'; c_enable <= '0'; c_reset <= '0'; m_enable <= '1'; q_enable <= '1'; q_mode <= '1'; e_enable <= '1'; start_ack <= '1'; data <= '0'; WHEN test => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN add => a_enable <= '1'; a_reset <= '1'; a_mode <= '1'; c_enable <= '1'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '0'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN test => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN add => a_enable <= '1'; a_reset <= '1'; a_mode <= '1'; c_enable <= '1'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '0'; e_enable <= '0'; start_ack <= '0'; data <= '0';

Copyright  1997 RASSP E&F 9494 Sequential Datapaths Example - 8 Bit Multiplier l Control unit output process (cont.) WHEN shift => a_enable <= '1'; a_reset <= '1'; a_mode <= '0'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '1'; q_mode <= '0'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN stop => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '1'; WHEN shift => a_enable <= '1'; a_reset <= '1'; a_mode <= '0'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '1'; q_mode <= '0'; e_enable <= '0'; start_ack <= '0'; data <= '0'; WHEN stop => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '1'; WHEN OTHERS => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; END CASE; END PROCESS controller_output; END synthesizable_behavior; WHEN OTHERS => a_enable <= '0'; a_reset <= '1'; a_mode <= '1'; c_enable <= '0'; c_reset <= '1'; m_enable <= '0'; q_enable <= '0'; q_mode <= '1'; e_enable <= '0'; start_ack <= '0'; data <= '0'; END CASE; END PROCESS controller_output; END synthesizable_behavior;

Copyright  1997 RASSP E&F 9797 RTL Level Synthesis l As stated previously, RLT level synthesis is synthesis from a level of abstraction above the logic level l In RTL level synthesis, the exact layout of the datapath is not specified l However, the designer must specify what happens on each clock edge - i.e., the registers must be implied in the behavioral code l Synthesis above this level, where registers are not implied by the behavioral code, is called behavioral synthesis

Copyright  1997 RASSP E&F 9898 RTL Level Synthesis Example - A Floating Point Multiplier l Example is a multiplier which multiplies two 32 bit floating point numbers to produce a 32 bit floating point result l The floating point format is as follows: m Decimal point is implied to the left of the 23 bit mantissa m There is an implied ‘1’ bit to the left of the decimal point so the mantissa is really 24 bits m Eight bit exponent is biased by 127 so positive and negative numbers can be represented m Single sign bit mantissa exponent sign 319810

Copyright  1997 RASSP E&F9 RTL Level Synthesis Floating Point Multiplier Functions l The multiplier functions consist of: m Splitting the inputs into their component parts - i.e., sign bit, exponent, mantissa m Computing the sign of the result m Adding the exponents m Multiplying the mantissas m Normalizing the result m Ronstructing the output from the above results l Each function will be performed in series by a separate process in the behavioral VHDL l A synchronous implementation is desired, so each process will be edge triggered by a global clock - although this is not required

Copyright  1997 RASSP E&F 100100 RTL Level Synthesis Floating Point Multiplier Flow Diagram Mult Mantissas Normalize Construct Output Separate Inputs Add Exponents Calculate Sign clk a_inputb_input 32 product 32 8 a_exponent b_exponent result_exponent result_mantissa 23 a_mantissa b_mantissa 48 8 8 result_sign normalized_mantissa normalized_exponent a_sign b_sign

Copyright  1997 RASSP E&F 101101 Floating Point Multiplier Code l Entity and architecture declarative part LIBRARY ieee; USE ieee.std_logic_1164.all; USE IEEE.numeric_std.all; ENTITY fp_multiplier IS PORT(clk : std_logic; a_input : IN unsigned(31 downto 0); b_input : IN unsigned(31 downto 0); product : OUT unsigned(31 DOWNTO 0)); END fp_multiplier; LIBRARY ieee; USE ieee.std_logic_1164.all; USE IEEE.numeric_std.all; ENTITY fp_multiplier IS PORT(clk : std_logic; a_input : IN unsigned(31 downto 0); b_input : IN unsigned(31 downto 0); product : OUT unsigned(31 DOWNTO 0)); END fp_multiplier; ARCHITECTURE synthesizable_behavior OF fp_multiplier IS CONSTANT bias : unsigned(7 DOWNTO 0) := "01111111"; CONSTANT two : unsigned(7 DOWNTO 0) := "00000010"; SIGNAL a_sign : std_logic; SIGNAL b_sign : std_logic; SIGNAL result_sign : std_logic; SIGNAL a_exponent : unsigned(7 DOWNTO 0); SIGNAL b_exponent : unsigned(7 DOWNTO 0); SIGNAL result_exponent : unsigned(7 DOWNTO 0); SIGNAL normalized_exponent : unsigned(7 DOWNTO 0); SIGNAL a_mantissa : unsigned(23 DOWNTO 0); SIGNAL b_mantissa : unsigned(23 DOWNTO 0); SIGNAL result_mantissa : unsigned(47 DOWNTO 0); SIGNAL normalized_mantissa : unsigned(47 DOWNTO 0); BEGIN ARCHITECTURE synthesizable_behavior OF fp_multiplier IS CONSTANT bias : unsigned(7 DOWNTO 0) := "01111111"; CONSTANT two : unsigned(7 DOWNTO 0) := "00000010"; SIGNAL a_sign : std_logic; SIGNAL b_sign : std_logic; SIGNAL result_sign : std_logic; SIGNAL a_exponent : unsigned(7 DOWNTO 0); SIGNAL b_exponent : unsigned(7 DOWNTO 0); SIGNAL result_exponent : unsigned(7 DOWNTO 0); SIGNAL normalized_exponent : unsigned(7 DOWNTO 0); SIGNAL a_mantissa : unsigned(23 DOWNTO 0); SIGNAL b_mantissa : unsigned(23 DOWNTO 0); SIGNAL result_mantissa : unsigned(47 DOWNTO 0); SIGNAL normalized_mantissa : unsigned(47 DOWNTO 0); BEGIN

Copyright  1997 RASSP E&F 102102 Floating Point Multiplier Code l Input and sign processes m Input process latches inputs into individual functional components - i.e., exponents, signs, mantissas m Sign process computes sign of result input : PROCESS BEGIN WAIT UNTIL rising_edge(clk); a_exponent(7 DOWNTO 0) <= a_input(8 DOWNTO 1); b_exponent(7 DOWNTO 0) <= b_input(8 DOWNTO 1); a_sign <= a_input(0); b_sign <= b_input(0); a_mantissa(22 DOWNTO 0) <= a_input(31 DOWNTO 9); a_mantissa(23) <= '1'; b_mantissa(22 DOWNTO 0) <= b_input(31 DOWNTO 9); b_mantissa(23) <= '1'; END PROCESS input; sign : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_sign <= a_sign xor b_sign; END PROCESS sign; input : PROCESS BEGIN WAIT UNTIL rising_edge(clk); a_exponent(7 DOWNTO 0) <= a_input(8 DOWNTO 1); b_exponent(7 DOWNTO 0) <= b_input(8 DOWNTO 1); a_sign <= a_input(0); b_sign <= b_input(0); a_mantissa(22 DOWNTO 0) <= a_input(31 DOWNTO 9); a_mantissa(23) <= '1'; b_mantissa(22 DOWNTO 0) <= b_input(31 DOWNTO 9); b_mantissa(23) <= '1'; END PROCESS input; sign : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_sign <= a_sign xor b_sign; END PROCESS sign;

Copyright  1997 RASSP E&F 103103 Floating Point Multiplier Code l Exponent and mantissa processes m Exponent process adds exponents and subtracts the bias m Mantissa process multiplies the mantissas - a combinational multiplier will be generated by the synthesis tool exponent : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_exponent <= a_exponent + b_exponent - bias; END PROCESS exponent; mantissa : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_mantissa <= a_mantissa * b_mantissa; END PROCESS mantissa; exponent : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_exponent <= a_exponent + b_exponent - bias; END PROCESS exponent; mantissa : PROCESS BEGIN WAIT UNTIL rising_edge(clk); result_mantissa <= a_mantissa * b_mantissa; END PROCESS mantissa;

Copyright  1997 RASSP E&F 104104 Floating Point Multiplier Code l Normalize process m Normalize process determines how many places to left shift mantissa result to place implied ‘1’ after the decimal point m It then shifts the mantissa result the required amount and subtracts the number of shifts to the exponent m The value of 2 is added to the exponent to account for the right shift when the implied ‘1’ was added to the left of the mantissas in the input process normalize : PROCESS VARIABLE count : NATURAL RANGE 48 DOWNTO 0; BEGIN WAIT UNTIL rising_edge(clk); count := 0; FOR i IN 47 DOWNTO 0 LOOP IF(result_mantissa(i) = '0') THEN count := count + 1; ELSE EXIT; END IF; END LOOP; count := count + 1;-- shift once more for implied '1' normalized_exponent <= result_exponent + two - to_unsigned(count,8); normalized_mantissa <= shift_left(result_mantissa,count); END PROCESS normalize; normalize : PROCESS VARIABLE count : NATURAL RANGE 48 DOWNTO 0; BEGIN WAIT UNTIL rising_edge(clk); count := 0; FOR i IN 47 DOWNTO 0 LOOP IF(result_mantissa(i) = '0') THEN count := count + 1; ELSE EXIT; END IF; END LOOP; count := count + 1;-- shift once more for implied '1' normalized_exponent <= result_exponent + two - to_unsigned(count,8); normalized_mantissa <= shift_left(result_mantissa,count); END PROCESS normalize;

Copyright  1997 RASSP E&F 105105 Floating Point Multiplier Code l Output process m Output process constructs the output product from the result sign, mantissa, and exponent output : PROCESS BEGIN WAIT UNTIL rising_edge(clk); product(31 DOWNTO 9) <= normalized_mantissa(47 DOWNTO 25); product(8 DOWNTO 1) <= normalized_exponent; product(0) <= result_sign; END PROCESS output; END synthesizable_behavior; output : PROCESS BEGIN WAIT UNTIL rising_edge(clk); product(31 DOWNTO 9) <= normalized_mantissa(47 DOWNTO 25); product(8 DOWNTO 1) <= normalized_exponent; product(0) <= result_sign; END PROCESS output; END synthesizable_behavior;

Copyright  1997 RASSP E&F 106106 Floating Point Multiplier Results - Overall Schematic

Copyright  1997 RASSP E&F 107107 Floating Point Multiplier Results - Adder Subcomponents

Copyright  1997 RASSP E&F 108108 Floating Point Multiplier Results - Subtractor Subcomponents

Copyright  1997 RASSP E&F 109109 Floating Point Multiplier Results - Multiplier Subcomponent

Copyright  1997 RASSP E&F 110110 Floating Point Multiplier Results - Shifter Subcomponent

Copyright  1997 RASSP E&F 111111 Floating Point Multiplier Post-Synthesis Simulation Results

Copyright  1997 RASSP E&F 113113 Structural VHDL l Structural VHDL is supported m Component declarations m Binding Indications m Component instantiations l Lower level components must be made of synthesizable constructs

Copyright  1997 RASSP E&F 114114 Structural VHDL And-Or-Invert Example l And gate, Or gate, and Inverter leaf cells LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY and2 is PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END and2; ARCHITECTURE behav OF and2 IS BEGIN c <= a and b; END behav; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY and2 is PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END and2; ARCHITECTURE behav OF and2 IS BEGIN c <= a and b; END behav; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY or2 is PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END or2; ARCHITECTURE behav OF or2 IS BEGIN c <= a or b; END behav; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY or2 is PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END or2; ARCHITECTURE behav OF or2 IS BEGIN c <= a or b; END behav; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY inv is PORT(a : IN std_logic; b : OUT std_logic); END inv; ARCHITECTURE behav OF inv IS BEGIN b <= not a; END behav; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY inv is PORT(a : IN std_logic; b : OUT std_logic); END inv; ARCHITECTURE behav OF inv IS BEGIN b <= not a; END behav;

Copyright  1997 RASSP E&F 115115 Structural VHDL And-Or-Invert Example l And-Or-Invert structural description m Entity m Architecture - component declarations LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY aoi2_str is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : OUT std_logic); END aoi2_str; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY aoi2_str is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : OUT std_logic); END aoi2_str; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY aoi2_str is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : OUT std_logic); END aoi2_str; ARCHITECTURE structural OF aoi2_str IS COMPONENT and2 PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END COMPONENT; COMPONENT or2 PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END COMPONENT; COMPONENT inv PORT(a : IN std_logic; b : OUT std_logic); END COMPONENT; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY aoi2_str is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : OUT std_logic); END aoi2_str; ARCHITECTURE structural OF aoi2_str IS COMPONENT and2 PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END COMPONENT; COMPONENT or2 PORT(a : IN std_logic; b : IN std_logic; c : OUT std_logic); END COMPONENT; COMPONENT inv PORT(a : IN std_logic; b : OUT std_logic); END COMPONENT;

Copyright  1997 RASSP E&F 116116 Structural VHDL And-Or-Invert Example l Architecture - binding indications, signal declarations, component instantiations FOR ALL : and2 USE ENTITY work.and2(behav); FOR ALL : or2 USE ENTITY work.or2(behav); FOR ALL : inv USE ENTITY work.inv(behav); SIGNAL and_out : std_logic;-- signal for output of and gate SIGNAL or_out : std_logic;-- signal for output of or gate BEGIN AND_1 : and2 PORT MAP(a => a, b => b, c => and_out); OR_1 : or2 PORT MAP(a => and_out, b => c, c => or_out); INV_1 : inv PORT MAP(a => or_out, b => d); END structural; FOR ALL : and2 USE ENTITY work.and2(behav); FOR ALL : or2 USE ENTITY work.or2(behav); FOR ALL : inv USE ENTITY work.inv(behav); SIGNAL and_out : std_logic;-- signal for output of and gate SIGNAL or_out : std_logic;-- signal for output of or gate BEGIN AND_1 : and2 PORT MAP(a => a, b => b, c => and_out); OR_1 : or2 PORT MAP(a => and_out, b => c, c => or_out); INV_1 : inv PORT MAP(a => or_out, b => d); END structural;

Copyright  1997 RASSP E&F 117117 Structural VHDL AOI Results Flatten and Optimize

Copyright  1997 RASSP E&F 119119 Implementation Technology Considerations l The developer of a synthesizable behavioral VHDL description MUST consider the implementation technology when writing the code m Efficiency reasons q Some FPGA technologies do not have built-in flip-flops, so registers or state variables are expensive q In some ASIC technologies multiplexors may in fact be faster that tri-states m Implementability reasons q Some FPGA families do not have internal tri-state devices - behavioral descriptions that are based on internal tri-state busses will fail in the technology mapping phase q Many PLDs have flip flops only on the I/O pins - state machines with too many I/O ports and state variable simply won’t fit

Copyright  1997 RASSP E&F 121121 Summary l This module presented the concept of hardware synthesis and how VHDL can be used to write synthesizable behavioral descriptions l Success with synthesis requires that the developer of the behavioral description think about what the synthesis tool is doing and try and drive it to the intended solution m Technology considerations - tri states vs. multiplexors, one-hot encoding vs. sequential, etc. m Tool limitations m Implementation libraries - combinational multipliers vs. sequential add/shift implementations, etc.

Copyright  1997 RASSP E&F 122122 Summary (cont.) l In reality, only the use of VHDL for RTL level and logic level synthesis was covered in this module l Tools for behavioral synthesis of VHDL descriptions are becoming available - Behavioral Complier for Synopsis, Monet from Mentor Graphics m It this time, these tools are still somewhat immature m Success with behavioral synthesis requires that the problem must be able to be case in the proper form - a data flow description m Behavioral synthesis tools are generally not appropriate for complex, control-flow dominated designs such as microprocessors or microcontrollers

Copyright  1997 RASSP E&F 123123 References [Parker84] Parker, Alice C., “Automated Synthesis of Digital Systems,” IEEE Design and Test of Computers, November 1984, pp. 75-81.

Copyright  1997 RASSP E&F 1 VHDL Synthesis Module 60 RASSP Education & Facilitation Program M60_01_00 February 1998 Copyright  1998 RASSP E&F All rights.

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Copyright  1997 RASSP E&F 1 VHDL Synthesis Module 60 RASSP Education & Facilitation Program M60_01_00 February 1998 Copyright  1998 RASSP E&F All rights.

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Presentation on theme: "Copyright  1997 RASSP E&F 1 VHDL Synthesis Module 60 RASSP Education & Facilitation Program M60_01_00 February 1998 Copyright  1998 RASSP E&F All rights."— Presentation transcript:

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