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Static Analysis of HDL Descriptions: Extracting Models for Verification Alexander Kamkin Sergey Smolov Igor Melnichenko.

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Presentation on theme: "Static Analysis of HDL Descriptions: Extracting Models for Verification Alexander Kamkin Sergey Smolov Igor Melnichenko."— Presentation transcript:

1 Static Analysis of HDL Descriptions: Extracting Models for Verification Alexander Kamkin Sergey Smolov Igor Melnichenko

2 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 2/14 Introduction Functional verification is a bottleneck of HW design process Different models are used for verification  Built from requirements  Extracted from HDL EFSM-based models are intensively used in verification

3 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 3/14 Extended Finite State Machine: FIFO example

4 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 4/14 Related work EFSM extraction for synthesis  Dependencies elimination [Giomi, 1995] EFSM extraction for functional test generation  Backtracking [Guglielmo et al., 2011] RTL-to-TLM abstraction in mutation testing  FAST framework [Bombieri et al., 2012]

5 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 5/14 EFSM extraction method Inner Representation elaboration IR-to-Guarded Action transformation Guarded Actions dataflow analysis EFSM building

6 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 6/14 Inner Representation-to-Guarded Action transformation Clock-like inputs analysis Splitting on “wait” statements For each process set is generated Guards – conditions of branches (if no such, ) Actions – branch statements

7 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 7/14 IR-to-GA transformation: example process (…) begin if clock’event then if reset = ‘1’ then state <= ‘0’; elsif en = ‘1’ then state <= state +‘1’; end if; count <= state; end process; C1 γ1 δ1 {clock} (reset = 1) state <= 0 C2 γ2 δ 2 {clock} !(reset=1)&&(en=1) state <= state + 1 C3 γ3 δ 3  true count <= state

8 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 8/14 Guarded Actions dataflow analysis Data Flow Graph – basic structure for state-like registers analysis

9 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 9/14 EFSM building (1)

10 EFSM building (2) Action1: Destination is: Action3: Guards for transitions: East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 10/14

11 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 11/14 Experiments EFSM extraction tool was implemented  JUNG – data flow graph analysis  ZamiaCAD – IR extraction 4 open-source VHDL designs were analyzed  42 modules, 14 KLOC  25% of modules – adequate EFSMs were extracted

12 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 12/14 Conclusion We have suggested the method for extracting EFSMs from HDL  Automated extraction of: clock inputs state registers We have successfully extracted EFSMs from HDL modules

13 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 13/14 Contacts Institute for System Programming RAS http://www.ispras.ru http://www.ispras.ru Hardware Verification Group http://hardware.ispras.ru Sergey Smolov ssedai@ispras.ru

14 East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 14/14 Thank you! Questions?

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