1. 1 Extending Atmel FPGA Flow Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013 - ESTEC

2. 2 Making Atmel FPGA Flow Work Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013 - ESTEC

3. 3 Outline Introduction FPGAs in Space Atmel FPGAs Atmel IDS Methodology Results Conclusion

4. 4 Field Programmable Gate Arrays General purpose configurable circuits o Compared to Application-Specific Integrated Circuits (ASICs) Pros o Rapid prototyping o Fixed cost per unit o Reprogrammability Cons o Lower performance o Higher power consumption

5. 5 FPGAs in Space Aforementioned advantages o Increased momentun in their usage in space Electronic circuits subject to radiation o Need for radiation hardening ITAR regulations o Increased bureaucracy o Preventing export to embargoed countries (e.g. China)

6. 6 Atmel FPGAs The only FPGA option that is o RAD-hard o ITAR-free  Suitable for ESA applications Many technologies available o 180nm AT58KRHA 180nm CMOS  ATF280 Family (used in this project) o AT40KEL040 350nm CMOS o ATFS450 150nm SOI  Available in the future

7. 7 Atmel IDS Atmel Integrated Development Systems (IDS) o Default software to program Atmel FPGAs o Provided by Atmel But, o Has not been significantly updated recently o Usability issues o Obsolete algorithms  Leaves much to be desired

8. 8 IDS Examples

9. 9 Outline Introduction Methodology Scope of the work Default flow Proposed flow VPLACE Experimental Setup Results Conclusion

10. 10 Scope of Work Improve IDS flow o Usability issues o Explore various implementation options Try alternative algorithms o VPLACE for placement Quantative evaluation o Use of various designs o Comparison between default IDS and VPLACE algorithms

11. 11 Default Flow Hardware specification o Hardware Description Language (HDL) Mentor Precision o Logic Synthesis Atmel IDS o Technology mapping o Placement o Routing o Bitstream Generation HDL Tech Mapping Placement Routing Bitstream Atmel IDS Netlist Mentor Precision Logic Synthesis

12. 12 Proposed Flow Automate the flow o Makefile usage o Constraint generation o Tool invocation o Optimize IDS options Replace IDS placement o Parse project DB o VPLACE placement o Update project DB Tech Mapping Placement Routing Bitstream Netlist HDL Mentor Precision Atmel IDS Logic Synthesis DB Parse Placement DB Update VPLACE Project DB

13. 13 VPLACE Academic algorithm for FPGA placement o Previously developed in Politecnico di Torino, Italy o Already used for Xilinx FPGAs Algorithm still not optimized for Atmel o Not timing-driven o Not tuned for Atmel architectures o But, already promising results Project database (DB) interface o Specifically developed during this project o Reverse-engineering of Atmel DB format (.fgd) o Around 3K C++ lines of code

14. 14 Experimental Setup Compare the two flows o Implementation targeting ATF280 FPGA family o IDS vs VPLACE placement o Compare performance (circuit period) Use of designs of interest o ITC ‘99 benchmarks (initial verification) o HurriCANe 5.2.4 (CAN bus) o Crf 0.90 (by Astrium Crisa)

15. 15 Outline Introduction Methodology Results ITC/HurriCANe CRF Conclusion

16. 16 Results 1/2 DesignIDSVPLACEDiff %DesignIDSVPLACEDiff % HurriCANe91.689.6-2.2 b019.230.1226.5b1020.827.934.1 b027.29.024.6b1135.1-N/A b0321.431.748.5b1257.554.5-5.5 b0443.542.7-1.9b1324.127.112.7 b0545.144.1-2.4b14156.4148.8-4.8 b069.017.493.8b14_1161.4160.4-0.6 b0724.730.222.2b15115.9115.8-0.0 b0834.239.214.7b15_1114.8120.55.0 b0928.533.517.4b17134.4151.012.39 Critical Period (ns)

17. 17 Results 2/2 Compare critical period of two runs o Different placement algorithms o VPLACE vs default IDS IDS pushed to maximum effort o Enabled timing-driven optimizations VPLACE still not optimized o Much way to go  Route congestion  Suboptimal results o But, already some improvement  Up to 5% for some ITC benchmarks  2.2% better for HurriCANe

18. 18 CRF Results Design by Astrium Crisa o Contact made during latest SEFUW (Nov 2012) o Provided only synthesized netlist  Flow does not necessarily need RTL anyway o Targeting AT40KEL040 family Desired frequency of 10 MHz o Crisa’s implementation had reached 4 MHz o Our flow reached 9.6 MHz (2.4x speedup)!  Just by using our default IDS flow  VPLACE does not support inout ports

19. 19 Conclusions Fully automated Atmel FPGA flow o More user friendly  Only few lines of configuration needed for each project o Unattended runs o Fast constraints exploration o Fine tuning of IDS options  Better results even than industrial attempts VPLACE algorithm o Alternative to default IDS placement o Still not optimized for Atmel  Not timing-driven  Not tuned for Atmel architecture o But, some promising results already

20. 20 Future Work Wait for newer version of VPLACE Try additional designs o SpaceWire o Other you suggest? Further exploration of IDS configuration options

21. 21 Thanks! Questions? nikos.andrikos@esa.int www.esa.int/TEC/Microelectronics/