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Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 4-1 Ders – 4: Davranışsal Modelleme.

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Presentation on theme: "Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 4-1 Ders – 4: Davranışsal Modelleme."— Presentation transcript:

1 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-1 Ders – 4: Davranışsal Modelleme

2 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-2 An initial Block  Executes exactly once during simulation  Starts at simulation time 0 reg x, y, z; initial begin // complex statement x = 1`b0; y = 1`b1; z = 1`b0; #10 x = 1`b1; y = 1`b1; z = 1`b1; end initial x = 1`b0; // single statement

3 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-3 An always block  Starts at simulation time 0  Executes continuously during simulation reg clock; initial clock = 1`b0; always #5 clock = ~clock;

4 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-4 Procedural Assignments  Syntax variable_lvalue = [timing_control] expression variable_lvalue <= [timing_control] expression [timing_control] variable_lvalue = expression [timing_control] variable_lvalue <= expression  Two types  blocking  nonblocking

5 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-5 Procedural Assignments  The bit widths  Keeping the least significant bits  Zero-extended in the most significant bits

6 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-6 Blocking Assignments  Are executed in the specified order  Use the “=“ operator // blocking assignments initial begin x = #5 1'b0; // at time 5 y = #3 1'b1; // at time 8 z = #6 1'b0; // at time 14 end

7 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-7 Blocking Assignments output reg [3:0] sum; output reg c_out; reg [3:0] t; always @(x, y, c_in) begin t = y ^ {4{c_in}}; {c_out, sum} = x + t + c_in; end Q: What is wrong with: t = y ^ c_in ? Q: Does a reg variable correspond to a memory element to be synthesized?

8 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-8 Nonblocking Assignments  Use the <= operator  Used to model several concurrent data transfers reg x, y, z; // nonblocking assignments initial begin x <= #5 1'b0; // at time 5 y <= #3 1'b1; // at time 3 z <= #6 1'b0; // at time 6 end

9 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-9 Nonblocking Assignments input clk; input din; output reg [3:0] qout; // a 4-bit shift register always @(posedge clk) qout <= {din, qout[3:1]}; // Right shift

10 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-10 Race Conditions // using blocking assignment statements always @(posedge clock) // has race condition x = y; always @(posedge clock) y = x; // using nonblocking assignment statements always @(posedge clock) // has no race condition x <= y; always @(posedge clock) y <= x;

11 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-11 Execution of Nonblocking Statements  Read  Evaluate and schedule  Assign

12 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-12 Blocking vs. Nonblocking Assignments // A 4-bit shift register always @(posedge clk) begin qout[0] = sin; qout[1] = qout[0]; qout[2] = qout[1]; qout[3] = qout[2]; end

13 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-13 Blocking vs. Nonblocking Assignments // A 4-bit shift register always @(posedge clk) begin qout[0] <= sin; qout[1] <= qout[0]; qout[2] <= qout[1]; qout[3] <= qout[2]; end

14 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-14 Blocking vs. Nonblocking Assignments  Suppose that count is 1 and finish is 0 before entering the always block always @(posedge clk) begin: block_a count = count – 1; if (count == 0) finish = 1; end always @(posedge clk) begin: block_b count <= count – 1; if (count == 0) finish <= 1; end Result: finish = 1. (Different from that of gate-level.) Result: finish = 0. (Same as that of gate-level.)

15 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-15 Coding Styles  blocking operators (=)  combinational logic  nonblocking operators (<=)  sequential logic

16 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-16 Delay Timing Control  Delay timing control  Regular delay control  Intra assignment delay control

17 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-17 Regular Delay Control  Regular delay control  Defers the execution of the entire statement reg x, y; integer count; #25 y <= ~x; // at time 25 #15 count <= count + 1; // at time 40

18 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-18 Intra-Assignment Delay Control  Intra-assignment delay control  Defers the assignment to the left-hand-side variable y = #25 ~x; // assign to y at time 25 count = #15 count + 1; // assign to count at time 40 y <= #25 ~x; // assign to y at time 25 count <= #15 count + 1; // assign to count at time 15

19 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-19 Event Timing Control  Edge-triggered event control  Named event control  Event or control  Level-sensitive event control Q: What is an event?

20 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-20 Edge-Triggered Event Control  Edge-triggered event control  @(posedge clock)  @(negedge clock) always @(posedge clock) begin reg1 <= #25 in_1; reg2 <= @(negedge clock) in_2 ^ in_3; reg3 <= in_1; end

21 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-21 Named Event Control  A named event event received_data; // declare always @(posedge clock) if (last_byte) -> received_data; // trigger always @(received_data) // recognize begin... end

22 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-22 Event or Control  Event or control  or ,  * or (*) means any signals always @(posedge clock or negedge reset_n) if (!reset_n) q <= 1`b0; else q <= d;

23 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-23 Level-Sensitive Event Control  Level-sensitive event control always wait (count_enable) count = count –1 ; always wait (count_enable) #10 count = count –1 ;

24 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-24 if…else Statement  Syntax if ( ) true_statement ; else false_statement; if ( ) true_statement1; else if ( ) true_statement2; else false_statement;

25 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-25 if…else Statement // using if…else statement always @(*) begin if (s1) begin if (s0) out = i3; else out = i2; end else begin if (s0) out = i1; else out = i0; end end

26 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-26 A Simple 4-bit Counter // the body of the 4-bit counter. always @(negedge clock or posedge clear) if (clear) qout <= 4'd0; else qout <= (qout + 1) ; // qout = (qout + 1) % 16;

27 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-27 case (casex/casez) Statement  Syntax case (case_expression) case_item1 {,case_item1}: procedural_statement1 case_item2 {,case_item2}: procedural_statement2... case_itemn {,case_itemn}: procedural_statementn [default: procedural_statement] endcase

28 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-28 A 4-to-1 MUX Example always @(I0 or I1 or I2 or I3 or S) case (S) 2'b00: Y = I0; 2'b01: Y = I1; 2'b10: Y = I2; 2'b11: Y = I3; endcase Q: Model a 3-to-1 multiplexer.

29 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-29 casex and casez Statements  casex and casez statements  Compare only non-x or z positions  casez treats all z values as don’t cares  casex treats all x and z values as don’t cares

30 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-30 casex and casez Statements // count the trailing zeros in a nibble always @(data) casex (data) 4'bxxx1: out = 0; 4'bxx10: out = 1; 4'bx100: out = 2; 4'b1000: out = 3; 4'b0000: out = 4; default: out = 3'b111; endcase Q: Is the default statement necessary?

31 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-31 while Loop  Syntax while (condition_expr) statement; while (count < 12) count <= count + 1; while (count <= 100 && flag) begin // put statements wanted to be carried out here end

32 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-32 while Loop // count the zeros in a byte integer i; always @(data) begin out = 0; i = 0; while (i <= 7) begin // simple condition if (data[i] == 0) out = out + 1; i = i + 1; end Q: Can the if … be replaced with out = out + ~data[i] ?

33 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-33 while Loop // count the trailing zeros in a byte integer i; always @(data) begin out = 0; i = 0; while (data[i] == 0 && i <= 7) begin // complex condition out = out + 1; i = i + 1; end

34 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-34 for Loop  Syntax for (init_expr; condition_expr; update_expr) statement; init_expr; while (condition_expr) begin statement; update_expr; end

35 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-35 for Loop // count the zeros in a byte integer i; always @(data) begin out = 0; for (i = 0; i <= 7; i = i + 1) // simple condition if (data[i] == 0) out = out + 1; end

36 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-36 for Loop // count the trailing zeros in a byte integer i; always @(data) begin out = 0; for (i = 0; data[i] == 0 && i <= 7; i = i + 1) out = out + 1; end

37 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-37 repeat Loop  Syntax repeat (counter_expr) statement; i = 0; repeat (32) begin state[i] = 0; i = i + 1; end repeat (cycles) begin @(posedge clock) buffer[i] <= data; i <= i + 1; end

38 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-38 forever Loop  Syntax forever statement; initial begin clock <= 0; forever begin #10 clock <= 1; #5 clock <= 0; end

39 Chapter 4: Behavioral Modeling Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 4-39 The forever Loop Structure reg clock, x, y; initial forever @(posedge clock) x <= y;

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