1. CENG 241 Digital Design 1 Lecture 5 Amirali Baniasadi amirali@ece.uvic.ca

2. 2 This Lecture zLab zReview of last lecture: Gate-Level Minimization zContinue Chapter 3:XOR functions, Hardware Description Language zHW 2: Due Thursday May 31st. zFIRST MIDTERM: THURSDAY JUNE 14, IN CLASS.

3. 3 Midterm 1 zCENG 241 Digital Design 1 Midterm #1 (sample) zImportant Note: Show your work for all sections. zConsider the following Boolean function: z F(A, B, C, D, E) = Σ (8,10,13,15,16,18,21,23,25,27) and d(A, B, C, D, E) = Σ (0,2,5,7,29,31) zUse the 1’s in the map to find the simplest Boolean function and implement it using only NAND gates. Draw the logic.(10 points) zUse the 0’s in the map to find the simplest Boolean function and implement it using only NOR gates. Draw the logic. (10 points) zNOTE: Each gate may have up to 3 inputs.

4. 4 zSum of Products and Product of Sums result in two level designs zNot all designs are two-level e.g., F=A.(C.D+B)+B.C’ zHow do we convert multilevel circuits to NAND circuits? zRules z 1-Convert all ANDs to NAND gates with AND-invert symbol z 2-Convert all Ors to NAND gates with invert-OR symbols z 3-Check the bubbles, insert bubble if not compensated Multilevel NAND circuits

5. 5 BC’ B’

6. 6 Multilevel NAND circuits

7. 7 Exclusive-OR Function X XOR Y = X’.Y+X.Y’ two input XOR IS 1 if both inputs are not similar

8. 8 Three-input XOR Function F = A XOR B XOR C Multiple input XOR is 1 only if the number of 1 variables is odd: ODD function

9. 9 ODD Function Implementation

10. 10 Four-input XOR Function F detects odd number of 1s, F’ detects even number of 1’s

11. 11 Parity Generation and Checking zParity bit: extra bit to ensure correct transmission of data zParity bit is included in the message to make the number of 1s either odd (odd parity) or even (even parity). zWe can use XOR to see if the number of 1’s is odd. zWe can use XOR-invert to see if the number of 1’s is even. zWe include the XOR output in the message zLater at receiver we check the number of 1 bits to see if the transmission is correct.

12. 12 Parity Generation and Checking circuits

13. 13 zHardware Description Language explains hardware in textual form zRepresents digital circuits zHDL has two applications: 1-Simulation: represents structure and behavior of digital circuits 2-Synthesis:Derives a list of components and interconnections from HDL. Two examples of HDL: VHDL, Verilog We use verilog since its easier to learn. Hardware Description Language

14. 14 Hardware Description Language-example //HDL Example 3-1 //-------------------------- //Description of the simple circuit of Fig. 3-37 module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y, C); or g3(x,e,y); endmodule

15. 15 //HDL Example 3-2 //--------------------------------- //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule Hardware Description Language-example How do we take into account gate delays?

16. 16 Test bench zTo simulate circuits we need input signals. zThe HDL description that provides the input/stimulus is called a test bench

17. 17 //HDL Example 3-3 //---------------------- //Stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay cwd(A,B,C,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C); endmodule Test bench example

18. 18 Test bench example simulation output

19. 19 Combinational Logic Combinational Logic: Output only depends on current input Sequential Logic:Output depends on current and previous inputs

20. 20 Design Procedure z1.The number of inputs and outputs? z2.Derive the truth table z3.Obtain the Boolean Function z4.Draw the logic diagram, verify correctness

21. 21 Design Procedure example zBinary Adder-Subtractor zBasic block is a half adder. zHalf Adder Design: z1.needs 2 inputs 2 outputs z2. Truth Table: x y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 z3. S=x’y+xy’ C=xy

22. 22 Half Adder circuit

23. 23 Full Adder? zTruth Table: zx y z C S z0 0 0 0 0 z0 0 1 0 1 z0 1 0 0 1 z0 1 1 1 0 z1 0 0 0 1 z1 0 1 1 0 z1 1 0 1 0 z1 1 1 1 1

24. 24 Full Adder Map

25. 25 Full Adder Circuit

26. 26 Full Adder Circuit Half adder ?

27. 27 4-bit Adder Circuit But this is slow...

28. 28 Summary zImplementation, XOR, Parity Checking, HDL zReading up to page 121-end of chapter 3 zHomework 2: problems 3-11, 3-15, 3-20, 3-23 and 3-24 from textbook