1. HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw}

2. Outline Introduction Timing analysis Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Discussion

3. Why Needs HDL-based Design Methodologies? ThenNow Schematic capture Component mapping & may be some logic optimization Place & route Layouts HDL design specification Synthesis Place & route Layouts Design complexity SW : assembly language => high-level language

4. An HDL-based Design Flow HDL coding styles Layout architectures Cell libraries HDL design specification RTL synthesis Logic synthesis Layout synthesis Layouts Applications

5. Top-Down Design Methodology Bridging the gap between RTL, logic, and layout synthesis Preserving design hierarchy HDL design specification RTL synthesis Logic synthesis Layout synthesis Layouts

6. Applications and Layout Architectures Datapath dominated designs : DSPs and processors. Control dominated designs: controllers and communication chips. Mixed type of designs. Bit-sliced stacks. Standard cells. Macro-cell-based. FPGAs.

7. Layout-driven Design methodology HDL design specification RTL synthesis Logic synthesis Layout synthesis Layouts Back annotation Multi-level estimation engine

8. Design Estimation Timing Area Power Statistic VS. quick-synthesis methods Analytical VS. constructive methods

9. Outline Introduction =>Timing analysis Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Summary

10. Minimum Cycle Time Critical path delay Clock skew

11. Timing Analysis Critical path delay analysis Clock skew analysis Timing analysis at different design levels Delay calculation Parasitic extraction Accuracy VS. fidelity

12. Timing Analysis HDL design spec. RTL synthesis Logic synthesis Layout synthesis Layouts HDL specification Logic equations Cell-based netlists (Tech. dependent or independent) Floorplanning and P & R Accuracy Complexity

13. RTL and Logic-level Timing Analysis Macro Inputs Outputs Logic equations Cell-based netlist Unit and zero delay models for cells and wires Macro based HDL Spec. Macro

14. RTL Timing Analysis HDL design spec. Macro A T Aspect ratio A T Aspect ratio 1 2 3 4 1 2 3 4 Floorplanning Back annotation Re-synthesis & re-floorplanning

15. Chip-level Timing Analysis Taken into account inter-macro wiring delays. Chip-level path enumeration. Estimation vs. back annotation. Macro cells Floorplanning Layout extraction Wiring delay

16. Macro-level Timing Analysis Taken into account intra-macro wiring delays. Path delay enumeration. Estimation vs. back annotation. Netlists P & R Layout extraction Wiring delay information

17. Accuracy of Timing Analysis Design Stages Floorplanning Placement Global routing Detailed routing Accuracy 100+/-25% 100+/-15% 100+/-7% 100+/-0% Source: DAC’97 Tutorial by Blaauw_Cong_Tsay RTL100+/-50%???

18. Outline Introduction Timing analysis => Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Summary

19. Design Planning Macro definitions Soft macro generation Macro placement Pin assignment

20. Chip Planning I Hard macros Soft macros

21. Chip Planning II Hard macros Soft macros

22. Design Planning Considerations How much timing, area, and power budgets should be assigned to each macro? How to generate soft macros? - top-down - bottom-up How to layout clock and power/ground network?

23. Design Budgeting Macro Load capacitance Required arrival time Driving resistance Arrival time RTL & Logic synthesis Netlists RTL Spec. Delay, area, power constraints ??????????????

24. Soft Macro Generation Design SM Clustering Partitioning Based on design hierarchical information

25. Soft Macro Generation (Cont.) Perform clustering techniques on a flattened netlist Clustering criteria:. Timing. Interconnect

26. Design Hierarchy Preservation Verilog design spec. HDL synthesis Macro formation Macro placement Macro to cell placement Initial placement HDLs Mod1 Mod2 Mod3

27. Clock Network Styles Mesh: robust, large area and power Trunk: simple Tree: min area, many supporting design algorithms

28. Clock Issues at RTL Critical path is determined from clock skew and skew cannot be determined until placement is completed! How to incorporate clock skew issues into early design planning???? Still an open problem!

29. RTL Timing Analysis HDL design spec. Macro A T Aspect ratio A T Aspect ratio 1 2 3 4 1 2 3 4 Floorplanning Back annotation Re-synthesis & re-floorplanning

30. Timing-critical Macro Detection HDL Spec. Macro HDL spec. Back annotation Floorplanning HDL synthesis Chip-level timing analysis Critical macro

31. RTL Design Planning HDL Spec. Macro Delay & area estimations Constructive or analytical method Cell library Floorplanning RTL timing analysis Back-annotation

32. Outline Introduction Timing analysis Design planning => RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Summary

33. RTL Design Budgeting RTL Spec. RTL/logic Synthesis Netlists Chip Layout Physical-level Synthesis Loop RTL sign-off HM SM3 HMSM1SM2 Area Delay Power Budget?

34. Timing Budgeting 1 Cycle Cross-macro timing paths!!!

35. Timing Budgeting Issues How to estimate delay and area from RTL specification??? After floorplanning? After RTL/logic synthesis? After placement? After routing? Run time VS. accuracy? How to distribute timing budget among macros? No much work has been done in this area!!!

36. Timing Budgeting for Design Optimization M1M2 M3 A T x A T x A T x Minimize total area subject to satisfying the timing constraints.

37. Outline Introduction Timing analysis Design planning RTL timing budgeting => A timing-driven soft-macro placement and resynthesis method Summary

38. A Typical Design Flow for Macro-based Design HDL Description HDL Synthesis Floorplanning P & R Timing Analysis OK? Chip Layout Back-annotation Yes No

39. Design Hierarchy Preservation HDL Description M1 M_11 M_12 M2 Preserving HDL design hierarchy for soft-macro placement? A complete chip design methodology? HM SM HM

40. Considerations How to utilize HDL design-hierarchy information to guide soft-macro placement procedure? How to integrate design tasks and point tools at different design level to form a complete chip design methodology? How to exploit the interaction between different design tasks.

41. Design Flow for Design Hierarchy Preservation HDL Description HDL Synthesis Floorplanning & Area Extraction P & R Pre-layout Timing Analysis Chip Layout Back-annotation Post-layout Timing Analysis SM Placement Structural-tree Construction SM Formation

42. Structural-tree Construction The main objective is to preserve the design structural information from an HDL design description for macro formation. Top HM1 HM2SM1SM2SM3SM4SM5 SM4,5 SM1,2

43. Soft macro Formation Decomposition of large soft macros. - A large macro is too rigid for macro placement. Clustering of small soft macros. - Many small macros increase the computational complexity.

44. Soft Macro Placement Inputs: a set of software macros and the available area for soft macros. Outputs: the relative location of each soft macro on the layout plane. 1st step: force-directed-based placement. 2nd step: Sweeping-based soft-macro assignment.

45. Floorplanning and Soft-Macro Area Extraction HM SM HM

46. Force-directed-based Placement HM SM1 SM2SM3 SM4

47. Soft-macro Placement SM1 SM2 SM3 SM4 X Y SM1 SM4SM2 SM3

48. The Experimental procedure: Design Synthesis HDL Description Synopsys (Design Compiler) Netlist Structural-tree Construction SM Formation

49. The Experimental Procedure: Floorplanning and P&R Netlist Cadence (Silicon Ensemble) SM PlacementCadence (HLDS) Cadence (Silicon Ensemble) Chip Layout

50. The Experimental Procedure: Timing Analysis Chip Layout Cadence (HyperExtract) AVANT! (STAR-DC) Synopsys (Design Time) Timing

51. Benchmarking Designs

52. Results

53. The Most Critical Path without Preserving Design Hierarchy

54. The Most Critical Path with Preserving Design Hierarchy

55. Resynthesis for Area/Delay Minimization HM SM3 HM SM1SM2 HM SM3 HMSM1SM2 Resynthesis for area minimization Resynthesis for delay minimization HM SM3 HMSM1SM2

56. Resynthesis-based Design Flow HDL Description HDL Synthesis Floorplanning SM Placement Timing Analysis Chip Layout P & R Yes No Resynthesis OK?

57. Slack Computation for Resynthesis Selection Macro FF p1 p2 p3 POS(SM_i) = Slack(p_j), for all Slack(p_j) > 0. NEG(SM_i) = Slack(p_j), for all Slack(p_j) < 0.

58. The Experimental Design Flow HDL Description HDL Synthesis Synopsys (Design Compiler) RC extraction AVANT! (STAR-RC) Timing analysis Synopsys (Design Time) Block placement Cadence (Silicon Ensemble) Chip Layout Resynthesis Synopsys (Design Compiler) Soft-macro placement Soft-macro Formation P & R AVANT! (Aquarious XO) Delay calculation AVANT! (STAR-RC) OK? yes no

59. Benchmarking Designs

60. Results (Ind2 using 0.5 um tech.)

61. Results (Ind2 using 0.25 um tech.)

62. Results (Ave. Gate Delay VS. Interconnect Delay of Ind2)

63. The Initial Critical Path of Ind2 using the 0.5um Library

64. The Critical Path of Ind2 after 2 Resynthesis Iterations

65. Discussion How to perform timing analysis at different design stages? Timing, area and power budgeting methods for early design planning? Performance-driven and power-driven chip design methodologies.