1. Verilog HDL: A solution for Everybody By, Anil Kumar Ram Rakhyani (akram@)

2. Traditional Design approaches Gate Level Design Schematic Design

3. Where is the problem? System specification is behavioral Manual Translation of design in Boolean equations Handling of large Complex Designs Can we still use SPICE for simulating Digital circuits?

4. Advancements over the years © Intel 4004 Processor Introduced in 1971 2300 Transistors 108 KHz Clock © Intel P4 Processor Introduced in 2000 40 Million Transistors 1.5GHz Clock

5. System Design Pyramid

6. History: Need: a simple, intuitive and effective way of describing digital circuits for modeling, simulation and analysis. Developed in 1984-85 by Philip Moorby In 1990 Cadence opened the language to the public Standardization of language by IEEE in 1995

7. A Match between Verilog & VHDL

8. A Match between Verilog & VHDL(con.)

9. Top-Down Design Approach

10. Definition of Module Interface: port and parameter declaration Body: Internal part of module Add-ons (optional)

11. Some points to remember The name of Module Comments in Verilog  One line comment (// ………….)  Block Comment (/*…………….*/) Description of Module (optional but suggested)

12. Description of Module

13. The Module Interface Port List Port Declaration

14. One language, Many Coding Style

15. One language, Many Coding Style (contd.)

17. Structural style: Verilog Code

18. Dataflow style: Verilog Code

19. Behavioral style: Verilog Code

20. Data Values and Representation Four Data value Data representation Type  Binary 6’b100101  Hex 6’h25

21. Class of Signals Nets: physical connection between hardware elements Registers: Store value even if disconnected

22. Nets wire/tri wand/triand wor/trior Supply0,supply1, tri0,tri1,trireg

23. Specifications of Ports

24. Registered Output

25. Delay Statement

26. Parameter

27. Test Bench module main; reg a, b, c; wire sum, carry; fulladder add(a,b,c,sum,carry); initial begin a = 0; b = 0; c = 0; #5 a = 0; b = 1; c = 0; #5 a = 1; b = 0; c = 1; #5 a = 1; b = 1; c = 1; #5 end endmodule

28. Memory Operation reg [31:0] register_file [0:7]; wire [31:0] rf_bus; wire r2b4; assign rf_bus = register_file [2]; assign r2b4 = rf_bus[4]; Can’t use register_file[2][4] for assigning value to variable r2b4

29. Some main points to remember Verilog is concurrent Think while writing your program. Blocking and Non-blocking Code

30. References: Evita_verilog Tutorial, www.aldec.comwww.aldec.com http://www.asic-world.com/verilog/