1. 數位系統實驗 Experiment on Digital System Lab05: IC design flow and FPGA Introduction to Verilog HDL 負責助教：葉俊顯 stanley

2. 2015/10/152 Outline IC Design Flow and FPGA Introduction to HDL Write Verilog code using Quartus II Lab

3. 2015/10/153 Outline IC Design Flow and FPGA Introduction to HDL Write Verilog code using Quartus II Lab

4. 2015/10/154 Digital system  數位系統 (digital system) 通常被設計用來實現或完成 某一些特殊的功能需求 MP3 player Mobile phone … 一個數位系統可能包含數個不同功能特質的數位電路， 而數位電路一般是使用所謂的半導體技術實作於積體電路 (Integrated circuit, IC) 上

5. 2015/10/155 IC design flow

6. 2015/10/156 ASIC and FPGA 當設計者完成 RTL(Register Transfer Level) 電路後，若使用製作 功能應用導向晶片 (Application Specific Integrated Circuit ， ASIC) 的 EDA tools 來進行合成、模擬、驗證，最後，會產生一個 GDS- II 檔案。最後，可將此檔案委請晶圓廠製成一顆 ASIC 晶片 FPGA/CPLD 是一種可依需要做程式規劃的晶片，其中包含許多 可被使用的 cells ，透過 FPGA 廠商提供的 FPGA-EDA tool 進行合 成、模擬與驗證，最後將所設計的電路燒錄到 FPGA 上面  FPGA (Field Programmable Gate Array) – 本課程所使用  CPLD (Complex Programmable Logic Device)

7. 2015/10/157 FPGA design flow

8. 2015/10/158 Outline IC Design Flow and FPGA Introduction to HDL Write Verilog code using Quartus II Lab

9. 2015/10/159 Introduction to HDL HDL  Hardware description language  Similar to general-purpose languages like C  Modeling and simulation of the functionality of combinational and sequential circuits  Parallel vs. sequential behaviors Two competitive forces  Verilog: C-like language – 本課程所使用  VHDL: ADA-like language

10. 2015/10/1510 Introduction to Verilog HDL C-like syntax/semantics Basic building block  Module Four kinds of model for circuits  Switch Level Model or Transistor Model (npn & pnp …)  Gate Level Model (or & and …)  Data Flow Model (assign)  Behavioral Model (RTL description) (always@() begin … end)

11. 2015/10/1511 Design hierarchy

12. 2015/10/1512 Identifier Names of modules, ports, wires and instances are all identifiers First character must be a letter, and other characters can be letters, numbers or underscore ( _ ) Upper case and lower case letters are different

13. 2015/10/1513 Keyword All keywords are defined in lower case

14. 2015/10/1514 Keyword All keywords are defined in lower case

15. 2015/10/1515 Data type net reg parameter

16. 2015/10/1516 Data type - net (wire)

17. 2015/10/1517 Data type - reg A reg data type represents a variable in Verilog Type ”reg” variable stores values, but not necessarily a FF (register) Are only assigned in an ”always” block task or function If a reg data type is assigned a value in an always block that has a clock edge expression, a flip-flop is inferred

18. 2015/10/1518 Data type - reg By default, net and register are one-bit wide

19. 2015/10/1519 Data type - parameter Represents constants Declared by: parameter data_size = 5; Cannot be changed at run time

20. 2015/10/1520 Value Set Verilog has four value levels

21. 2015/10/1521 Operator Priority

22. 2015/10/1522 Module

23. 2015/10/1523 Module - example module half_adder ( x, y, c, s ); // port declaration input x; // width: 1 bit input y; output c, s; // I/O type and data type wire c; wire s; // functionality or structure xor (s, x, y); // (out, in, ……) and (c, x, y); endmodule module name port name Verilog primitive

24. 2015/10/1524 Circuit design using - Four kinds of model Switch Level Model Gate Level Model Data Flow Model Behavioral Model

25. Example: Half adder 25 module half_adder ( //input x, y, //output c, s ); // port declaration input x; // width: 1 bit input y; output c, s; // I/O type and data type wire c; wire s; // functionality or structure xor (s, x, y); and (c, x, y); endmodule assign s=x^y; assign c=x&y; reg s,c; always @(x or y) begin s=x^y; c=x&y; end Data Flow Model Behavioral Model Gate Level Model

26. Example: Full adder (Gate Level Model) 26 module full_adder (x, y, z, S, C); input x, y, z; output S, C; // internal nets/registers wire wire01; wire wire02; wire wire03; // functionality or structure xor xor01(wire01, x, y); and and01(wire02, x, y); xor xor02(S, wire01, z); and and02(wire03, wire01, z); or (C, wire02, wire03); endmodule

27. Example: Full adder (2HA+1OR) 27 module full_adder (x, y, z, S, C); input x, y, z; output S, C; wire wire1, wire2, wire3 ; // functionality or structure // module instantiations half_adder ha1( //input.x (x),.y (y), //output.c (wire2),.s (wire1) ); half_adder ha2( //input.x (wire1),.y (z), //output.c (wire3),.s (S) ); or (C, wire2, wire3); endmodule

28. Instantiation and port mapping 28 In order By name // in half_adder.v half_adder (x, y, c, s); // in full_adder.v half_adder ha1(x, y, wire2, wire1); half_adder ha2(wire1, z, wire3, s); // in half_adder.v half_adder (x, y, c, s); // in full_adder.v half_adder ha1(.x(x),.y(y),.c(wire2),.s(wire1)); half_adder ha2(.x(wire1),.y(z),.s(s),.c(wire3));

29. 2015/10/1529 Outline IC Design Flow and FPGA Introduction to HDL Write Verilog code using Quartus II Lab

30. Step by Step Getting Started –  Start the Quartus II software 30

31. 31 Create a New Project –  Open New Project Wizard (File → New Project Wizard…) Step by Step

32. 32 Specify the working directory and the name of the project 可先新增資料夾 請記住 ! Step by Step

33. 33 Select design files. Or click “Next” to skip this step Specify device settings - (Here we use the VerLite Device family) EP1C6Q240C8 Step by Step

34. 34 Edit a Schematic File Open a new Verilog HDL file  (File → New → Verilog HDL File → OK) Step by Step

35. 35 Write Verilog code Top module name 一定要跟 Project name 相同 !! Step by Step 輸入 (input) 輸出 (output) 被加數 (a) 加數 (b) 和 (sum) 進位 (carry) 0000 0110 1010 1101 1: //File Name ： Half_Adder.v 2: moduleHalf_Adder(a, b, sum, carry); 3: inputa, b; 4: outputsum, carry; 5: 6: assign sum = a ^ b; 7: assign carry = a & b; 8: 9: endmodule

36. 36 Compiling the Designed Circuit  (Processing → Start Compilation) Step by Step

37. 37 Successful compilation Step by Step

38. Simulating the Designed Circuit  Using the Waveform Editor (File → New → Vector Waveform File) 38 Step by Step

39. Simulating the Designed Circuit  Use node finder to find all the pins (Edit → Insert → Insert Node or Bus…) 39 Step by Step

40. Simulating the Designed Circuit  Selecting nodes to insert into the Waveform Editor Step by Step 40 沒跑出 pin 腳，表示你剛剛忘記 compile

41. Simulating the Designed Circuit  Selecting nodes to insert into the Waveform Editor Step by Step 41

42. Simulating the Designed Circuit  Select and edit waveform Step by Step 42

43. Simulating the Designed Circuit  Setting of test values Step by Step 43

44. Performing the Simulation  Modify default settings (Assignments → Settings… → Simulator Settings → Functional → OK) Step by Step 44

45. Generate functional simulation netlist before simulation (Processing → Generate Functional Simulation Netlist) Step by Step 45

46. Start simulation (Processing → Start Simulation ) Step by Step 46

47. The result of functional simulation Step by Step 47 輸入 (input) 輸出 (output) 被加數 (a) 加數 (b) 和 (sum) 進位 (carry) 0000 0110 1010 1101

48. 2015/10/1548 Outline IC Design Flow and FPGA Introduction to HDL Write Verilog code using Quartus II Lab

49. Lab I Using Verilog to implement a 1-bit Full Adder Simulation Result zyxSC 00000 00110 01010 01101 10010 10101 11001 11111 49

50. Lab I - Hint Hint (Gate Level Model) 50

51. Lab II Using Verilog to implement a 2-bit Full Adder Simulation Result z1y1x1C1y2x2S1S2C2 000000000 001001110 010010110 011100010 100011101 101101001 110110001 111111111 51

52. Lab II - Hint x1 y1 z1 S1 C1 x2 y2 S2 C2 wire01 wire02 wire03 wire04 wire05 wire06 or01 or02 xor03 xor04 and03 and04 X C1 52 Ref. Instantiation and port mapping

53. Notice 請勿在桌面建立 Project 及請勿命名中文資料夾 Device family 請確認與 FPGA Chip 符合 (EP1C6Q240C8) Top module name & Project name 需要一致 確認 module … endmodule 為 keyword 變成藍色字體 53