1. 1 COMP541 Combinational Logic - I Montek Singh Jan 11, 2012

2. 2Today  Basics of digital logic (review) Basic functions Basic functions Boolean algebra Boolean algebra Gates to implement Boolean functions Gates to implement Boolean functions

3. 3 Binary Logic  Binary variables Can be 0 or 1 (T or F, low or high) Can be 0 or 1 (T or F, low or high) Variables named with single letters in examples Variables named with single letters in examples Really use words when designing circuits Really use words when designing circuits

4. Logic Gates  Perform logic functions: inversion (NOT), AND, OR, NAND, NOR, etc. inversion (NOT), AND, OR, NAND, NOR, etc.  Single-input: NOT gate, buffer NOT gate, buffer  Two-input: AND, OR, XOR, NAND, NOR, XNOR AND, OR, XOR, NAND, NOR, XNOR  Multiple-input

5. Single-Input Logic Gates

6. Two-Input Logic Gates

7. More Two-Input Logic Gates

8. Multiple-Input Logic Gates

9. NAND is Universal  Can express any Boolean Function  Equivalents below 9

10. Using NAND as Invert-OR  Also reverse inverter diagram for clarity 10

11. NOR Also Universal  Dual of NAND 11

12. Representation: Schematic 12

13. Representation: Boolean Algebra  More on this next time 13

14. Representation: Truth Table  2 n rows: where n # of variables 14

15. 15 Schematic Diagrams  Can you design a Pentium or a graphics chip that way? Well, yes, but diagrams are overly complex and hard to enter Well, yes, but diagrams are overly complex and hard to enter  These days people represent the same thing with text (code)

16. Hardware Description Languages  Main ones are Verilog and VHDL Others: Abel, SystemC, Handel Others: Abel, SystemC, Handel  Origins as testing languages To generate sets of input values To generate sets of input values  Levels of use from very detailed to more abstract descriptions of hdw Think about C++ from assembly level description to very abstract HLL Think about C++ from assembly level description to very abstract HLL 16

17. Design w/ HDL  Two leading HDLs: Verilog Verilog  developed in 1984 by Gateway Design Automation  became an IEEE standard (1364) in 1995 VHDL VHDL  Developed in 1981 by the Department of Defense  Became an IEEE standard (1076) in 1987  Most (all?) commercial designs built using HDLs  We’ll use Verilog

18. Uses of HDL  Simulation Defines input values are applied to the circuit Defines input values are applied to the circuit Outputs checked for correctness Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Millions of dollars saved by debugging in simulation instead of hardware  Synthesis Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them)IMPORTANT: When describing circuits using an HDL, it’s critical to think of the hardware the code should produce. When describing circuits using an HDL, it’s critical to think of the hardware the code should produce.

19. Verilog Module  Code always organized in modules  Represent a logic “box” With inputs and outputs With inputs and outputs 19

20. Example module example(input a, b, c, output y); output y); *** HDL CODE HERE *** *** HDL CODE HERE ***endmodule 20

21. 21 Levels of Verilog Several different levels (or “views”) Structural Structural Dataflow Dataflow Conditional Conditional Behavioral Behavioral Look at first three today

22. 22 Example 1  Output is 1 when input < 011

23. 23 Structural Verilog  Explicit description of gates and connections  Textual form of schematic  Specifying netlist

24. 24 Example 1 in Structural Verilog module example_1(X,Y,Z,F); input X; input X; input Y; input Y; input Z; input Z; output F; output F; //wire X_n, Y_n, Z_n, f1, f2; not g0(X_n, X), g1(Y_n, Y), g2(Z_n, Z); nand g3(f1, X_n, Y_n), g4(f2, X_n, Z_n), g5(F, f1, f2); endmodule Can also be input X, Y, Z;

25. Slight Variation – Gates not named 25 module example_1_c(X,Y,Z,F); input X; input X; input Y; input Y; input Z; input Z; output F; output F; not(X_n, X); not(Y_n, Y); not(Z_n, Z); nand(f1, X_n, Y_n); nand(f2, X_n, Z_n); nand(F, f1, f2); endmodule

26. 26Explanation  Each of these gates is an instance Like object vs class Like object vs class  In first example, they had names not g0(X_n, X),  In second example, no name not(X_n, X);  Later see why naming can be useful

27. 27Gates  Standard set of gates available and, or, not and, or, not nand, nor nand, nor xor, xnor xor, xnor buf buf

28. 28 Dataflow Description  Basically a logical expression  No explicit gates module example_1_b(X,Y,Z,F); input X; input Y; input Z; output F; assign F = (~X & ~Y) | (~X & ~Z); endmodule

29. Conditional Description module example_1_c(input [2:0] A, output F); assign F = (A > 3’b011) ? 0 : 1; endmodule 29 Notice alternate specification

30. Abstraction  Using the digital abstraction we’ve been thinking of the inputs and outputs as True or False True or False 1 or 0 1 or 0  What are they really? 30

31. Logic Levels  Define discrete voltages to represent 1 and 0  For example, we could define: 0 to be ground or 0 volts 0 to be ground or 0 volts 1 to be V DD or 5 volts 1 to be V DD or 5 volts  What about 4.99 volts? Is that a 0 or a 1?  What about 3.2 volts?

32. Logic Levels  Define a range of voltages to represent 1 and 0  Define different ranges for outputs and inputs to allow for noise in the system  What is noise?

33. What is Noise?  Anything that degrades the signal E.g., resistance, power supply noise, coupling to neighboring wires, etc. E.g., resistance, power supply noise, coupling to neighboring wires, etc.  Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts 33

34. The Static Discipline  Given logically valid inputs, every circuit element must produce logically valid outputs  Discipline ourselves to use limited ranges of voltages to represent discrete values

35. Logic Levels

36. Noise Margins NM H = V OH – V IH NM L = V IL – V OL

37. DC Transfer Characteristics Ideal Buffer: Real Buffer: NM H = NM L = V DD /2 NM H, NM L < V DD /2

38. V DD Scaling  Chips in the 1970’s and 1980’s were designed using V DD = 5 V  As technology improved, V DD dropped Avoid frying tiny transistors Avoid frying tiny transistors Save power Save power  3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …

39. Logic Family Examples Logic FamilyV DD V IL V IH V OL V OH TTL5 (4.75 - 5.25)0.82.00.42.4 CMOS5 (4.5 - 6)1.353.150.333.84 LVTTL3.3 (3 - 3.6)0.82.00.42.4 LVCMOS3.3 (3 - 3.6)0.91.80.362.7

40. Reading  Textbook Ch. 2.1 – 2.6 40