1. HDL Bencher FPGA Design Workshop

2. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to:  Describe the process to create a testbench for HDL designs  Reduce testing time by integrating HDL Bencher into Digital Design Labs

3. For Academic Use Only Presentation Name 3 Outline  Overview  Create a New Source  Create Waveforms  Export Testbench  Summary

4. For Academic Use Only Presentation Name 4 HDL Bencher  Creates timing constrained VHDL and Verilog self-checking testbenches  No knowledge of HDL or scripting required

5. For Academic Use Only Presentation Name 5 Overview  HDL Bencher helps validate design function and performance  HDL Bencher generates – VHDL or Verilog testbenches – Design specific waveforms – Documentation  Testbenches can be simulated with various simulators – Model Technology – Synopsys

6. For Academic Use Only Presentation Name 6 Advantages  No HDL or scripting knowledge required (or even needed!)  No need to manually modify testbenches for each design revision

7. For Academic Use Only Presentation Name 7 How It Works  Step 1: Create New Source  Step 2: Draw stimulus and response waveforms  Step 3: Export testbench

8. For Academic Use Only Presentation Name 8 Outline Overview Create a New Source Create Waveforms Export Testbench Summary

9. For Academic Use Only Presentation Name 9 Create a New Source

10. For Academic Use Only Presentation Name 10 HDL Bencher Unit under test is analyzed, when selected – Port problems – Syntax violations – Inconsistencies Design timing selected – Specify clock timing – Single, multiple, or internal clocks

11. For Academic Use Only Presentation Name 11 HDL Bencher

12. For Academic Use Only Presentation Name 12 HDL Bencher Windows  Title bar  Process bar  Port direction  Line numbers  Menu  Waveform window  Waveforms  HDL source editor

13. For Academic Use Only Presentation Name 13 Outline Overview Create a New Source Create Waveforms Export Testbench Summary

14. For Academic Use Only Presentation Name 14 Create Waveforms  Data values – 1, 0,X,Z, U  Assignments – Double-click bit signal to toggle value – Pattern wizard assigns a range of cell values – WaveTable assign signals like a spreadsheet – By default, decimal values are shown in the WaveTable  Waveform values are checked as they are entered – Validation check for non-binary inputs only (for example, hex, or decimal)

15. For Academic Use Only Presentation Name 15 Toggling  Toggling bit values is the easiest way to assign bit signals  Simply click directly on the signal’s waveform at the time where changes should take place Click directly on these boxes, at the time where signals should toggle

16. For Academic Use Only Presentation Name 16 WaveTable  Intended for fast behavioral verification  Waveforms represented as cells  Data entered in spreadsheet format  Double-click a signal at the time it should be changed, to access value cell editor  Enter value and press Return for the next time frame  Range validation checked after each entry Double-click in this area Enter values in this area

17. For Academic Use Only Presentation Name 17 Pattern Wizard  Aids complex waveform input  To access, click a signal at the time it should be changed to access value cell editor  Note: light blue background = input assignment,  light yellow background = output assignment Click in this area Click here for Pattern Wizard

18. For Academic Use Only Presentation Name 18 Pattern Wizard  Available patterns  Pattern description – Changes depending on the pattern selected  Count unit in clock cycles

19. For Academic Use Only Presentation Name 19 Outline  Overview  Create a New Source  Create Waveforms  Export Testbench  Summary

20. For Academic Use Only Presentation Name 20 Testbench  Translates waveforms to testbenches  Writes out VHDL or Verilog testbench  Color-coded for easy reading and reference  Includes – Library extractions – Log file creation – Procedure check – Input assignments – Output validation – Defined test signals – Delay verification – UUT (Unit Under Test) instantiation

21. For Academic Use Only Presentation Name 21 Configuration Options  Configuration Ability to automatically terminate the testbench for export on the last assignment VHDL compliance

22. For Academic Use Only Presentation Name 22 Testbench Waveform file extensions are TBW Waveform file can be seen in the Sources in Project window of the Project Navigator To view testbench: – In Sources in Project Window, select the TBW file – Then in the Processes for Current Source window, click View Behavioral Testbench

23. For Academic Use Only Presentation Name 23 Outline  Overview  Create a New Source  Create Waveforms  Export Testbench  Summary

24. For Academic Use Only Presentation Name 24 Summary  HDL Bencher helps validate design function and performance  The three steps to create a testbench are – Create a new source – Develop waveforms – Export testbench  Writes out VHDL or Verilog testbench

25. For Academic Use Only Presentation Name 25 Where Can I learn More? The HDL Bencher tool – Help Menu – support.xilinx.com  software manuals  Development System Reference Guide  HDL Bencher Help