1. 1 COMP541 Combinational Logic - 3 Montek Singh Jan 21, 2010

2. Topics 2  Other gates, XOR  X’s – don’t cares Using encoder as example Using encoder as example  Z’s – floating values  Multiplexers and Decoders  Quick look at timing and glitches

3. Other Types of Gates 3  In practical terms, doesn’t matter for our FPGA But does for other technologies But does for other technologies

4. Exclusive OR 4  Exclusive OR  What lay people mean by “or”  Symbol is  Plus in a circle Plus in a circle

5. Parity Function 5  Recall how parity works Ask class Ask class  Write truth table for two input even parity What needs to be generated for parity bit? What needs to be generated for parity bit?  What function of two inputs gives you this?

6. XOR Gives Odd Function 6  As many inputs as necessary  How do you get odd parity?  Design even parity generator for 3-bit signal Perhaps make truth table and K-Map Perhaps make truth table and K-Map Draw with XOR, then sum-of-products w/ NAND gates Draw with XOR, then sum-of-products w/ NAND gates  How do you design a detector?  How about a 7-bit ASCII character?

7. Others 7

8. CMOS Transmission Gates 8  Act like electronic switches

9. XOR w/ Transmission Gate 9

10. Introduction to Circuits 10  A logic circuit is composed of: Inputs Inputs Outputs Outputs Functional specification Functional specification Timing specification Timing specification

11. Circuits  Nodes Inputs: A, B, C Inputs: A, B, C Outputs: Y, Z Outputs: Y, Z Internal: n1 Internal: n1  Circuit elements E1, E2, E3 E1, E2, E3 Each a circuit Each a circuit 11

12. Types of Logic Circuits  Combinational Logic Memoryless Memoryless Outputs determined by current values of inputs Outputs determined by current values of inputs  Sequential Logic Has memory Has memory Outputs determined by previous and current values of inputs Outputs determined by previous and current values of inputs 12

13. Rules of Combinational Composition Composition rules: Every circuit element is itself combinational Every circuit element is itself combinational Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element  no output shorts The circuit contains no cyclic paths The circuit contains no cyclic paths  every path through the circuit visits each circuit node at most once (latches are made via a cyclic path) Example: Example: 13

14. Aside: Circuit Schematics with Style 14 Drawing style/conventions: (where possible) Inputs are on the left (or top) side of a schematic Inputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a schematic Outputs are on the right (or bottom) side of a schematic Gates should flow from left to right Gates should flow from left to right Straight wires are better to use than jagged wires Straight wires are better to use than jagged wires

15. Circuit Schematic Rules (cont.) Wire connections A dot where wires cross indicates a connection A dot where wires cross indicates a connection Wires crossing without a dot make no connection Wires crossing without a dot make no connection Wires always connect at a T junction Wires always connect at a T junction 15

16. Multiple Output Circuits Output asserted corresponding to most significant TRUE input 16

17. Priority Encoder Hardware 17

18. Don’t Cares (X) 18

19. Meanings of X 19  Don’t care  Contention (illegal input value)  Uninitialized value In a simulator In a simulator

20. Floating: Z  Floating, high impedance, open, high Z Floating output might be 0, 1, or somewhere in between Floating output might be 0, 1, or somewhere in between A voltmeter won’t indicate whether a node is floating A voltmeter won’t indicate whether a node is floating Allows connecting outputs Allows connecting outputs Tristate Buffer 20

21. Combinational Building Blocks  Multiplexers  Decoders  Encoders 21

22. Multiplexer (Mux) 22  Selects between one of N inputs to connect to the output.  log 2 N-bit select input – control input  Example: 2:1 Mux

23. Multiplexer Implementations  Logic gates Sum-of-products form Sum-of-products form  Tristates For an N-input mux, use N tristates For an N-input mux, use N tristates Turn on exactly one to select the appropriate input Turn on exactly one to select the appropriate input

24. Multiplexer with Hi-Z 24 Normal operation is blue area Smoke

25. Logic using Multiplexers  Using the mux as a lookup table

26. Verilog for Multiplexer 26  Just a conditional statement. For example, module mux2(input [3:0] d0, d1, input s, input s, output [3:0] y); output [3:0] y); assign y = s ? d1 : d0; assign y = s ? d1 : d0;endmodule

27. Decoders  N inputs, 2 N outputs  “One-hot” outputs only one output HIGH at any time only one output HIGH at any time

28. Decoder Implementation

29. Aside: Enable  Enable is a common input to logic functions  See it in memories and today’s logic blocks 29

30. 2-to-4 Decoder with Enable 30

31. Verilog 31

32. Decoders  How about a… 1-to-2 decoder? 1-to-2 decoder? 3-to-8 decoder? 3-to-8 decoder? (N+1)-to-2 (N+1) decoder? (N+1)-to-2 (N+1) decoder? 32

33. 3-to-8 Decoder: Truth Table  Notice they are minterms 33

34. 3-to-8 Decoder: Schematic 34

35. 3-to-8 Decoder: Multilevel Circuit 35

36. 3-to-8 Decoder: Enable used for expansion 36

37. Multi-Level 6-to-64 Decoder 37

38. Uses for Decoders  Binary number might serve to select some operation  CPU op codes are encoded Decoder lines might select add, or subtract, or multiply, etc. Decoder lines might select add, or subtract, or multiply, etc.  Memory address lines 38

39. Logic using Decoders  OR the ON-set minterms

40. Demultiplexer  Takes one input  Out to one of 2 n possible outputs 40

41. Demux is a Decoder  With an enable 41

42. Encoder  Encoder is the opposite of decoder  2 n inputs (or fewer)  n outputs 42

43. Truth Table 43

44. Inputs are Minterms  Can OR them together appropriately  A 0 = D 1 + D 3 + D 5 + D 7 44

45. What’s the Problem?  What if D3 and D6 both high?  Simple OR circuit will set A to 7 45

46. Priority Encoder  Chooses one with highest priority Largest number, usually Largest number, usually  Note “don’t cares” 46 What if all inputs are zero?

47. Need Another Output  A “Valid” output 47

48. Valid is OR of inputs 48

49. Code Converters  One code to another  Book puts seven-segment decoder in this category  Typically multiple outputs Each output has function or truth table Each output has function or truth table 49

50. Seven-Segment Decoder  LAST Friday’s lab: Verilog of hex to LEDs  Extended version of book example 50

51. Timing  What is Delay? Time from input change to output change Time from input change to output change  Transient response e.g., rising edge to rising edge e.g., rising edge to rising edge Usually measured from 50% point Usually measured from 50% point

52. Delays  Transport delay = “pure” delay Output after a specified time Output after a specified time  Inertial delay No effect if input occurs for time that is too short (can’t overcome inertia) No effect if input occurs for time that is too short (can’t overcome inertia)  can filter out glitches 52

53. Effect of Transport Delay (blue)  Delay just shifts signal in time focus on the blue bars; ignore the black ones focus on the blue bars; ignore the black ones 53

54. Effect of Inertial Delay 54 Blue – Propagation delay time Black – Rejection time

55. Propagation & Contamination Delay  Propagation delay: t pd max delay from input to output max delay from input to output  Contamination delay: t cd min delay from input to output min delay from input to output

56. Propagation & Contamination Delay  Delay is caused by Capacitance and resistance in a circuit Capacitance and resistance in a circuit  More gates driven, longer delay  Longer wires at output, longer delay Speed of light is the ultimate limitation Speed of light is the ultimate limitation  Reasons why t pd and t cd may be vary: Different rising and falling delays Different rising and falling delays  What is typically reported? Greater of the two Multiple inputs and outputs, some faster than others Multiple inputs and outputs, some faster than others Circuits slow down when hot and speed up when cold Circuits slow down when hot and speed up when cold  So, both maximum and typical given  Specs provided in data sheets

57. Propagation & Contamination Delay 57

58. Critical (Long) Path: t pd = 2t pd_AND + t pd_OR Short Path: t cd = t cd_AND Critical and Short Paths Critical (Long) and Short Paths

59. Glitches  What is a Glitch? a non-monotonic change in a signal a non-monotonic change in a signal e.g., a single input change can cause multiple changes on the same output e.g., a single input change can cause multiple changes on the same output a multi-input transition can also cause glitches a multi-input transition can also cause glitches  Are glitches a problem? Not really in synchronous design Not really in synchronous design  Clock time period must be long enough for all glitches to subside Yes, in asynchronous design Yes, in asynchronous design  Absence of clock means there should ideally be no spurious signal transitions, esp. in control signals It is important to recognize a glitch when you see one in simulations or on an oscilloscope It is important to recognize a glitch when you see one in simulations or on an oscilloscope Often cannot get rid of all glitches Often cannot get rid of all glitches

60. Glitch Example  What happens when: A = 0, C = 1, and A = 0, C = 1, and B goes from 1 to 0? B goes from 1 to 0?  Logically, nothing Because although 2nd term goes to false Because although 2nd term goes to false 1st term now is true 1st term now is true  But, output may glitch if one input to OR goes low before the other input goes high if one input to OR goes low before the other input goes high

61. Glitch Example (cont.)

62. Fixing the Glitch  Add redundant logic term

63. Next  Hierarchical Design 63