1. Limitations of Digital Computation William Trapanese Richard Wong

2. Fundamental Limit Irreversible Logic Device First developed by John von Neumann over 50 years ago and discussed in depth by Rolf Landauer in 1961 First developed by John von Neumann over 50 years ago and discussed in depth by Rolf Landauer in 1961 Entropy caused by changing states defined by Boltzmann Principle that: S = k B ln Ω Where S = entropy and Ω is number of states The energy required to overcome this entropy is: ΔE = T ΔS E = T k B ln Ω Since digital logic is binary (Ω = 2) and the energy needed to change a bit is: E = k B T ln 2

3. Fundamental Limit From this equation known as the von Neumann – Landauer expression limits of other properties arise E bit ≥ k B T ln 2 =.017 eV. Use the uncertainity relations to determine the minimum limits of the size, density, power and speed of a digital switching device?

4. Fundamental Limit Δx Δp ≥ ħ ΔE Δt ≥ ħ x min = ħ / Δp = ħ / (2 m e E bit ).5 = 1.5nm Where x min is the minimum size of a switch n max = 1 / x 2 = 4.7 x 10 13 devices / cm 2 Where n max is the maximum density of switches t min = ħ / ΔE =.04 ps Where t min is the minimum switching time Speed = 1 / t min = 1/.04 = 2.5 x 10 13 hz P = ( n max E bit ) / t min = 3.7 x 10 6 W / cm 2

5. Fundamental Limit The Fundamental Limit Depends on using mobile electron carriers to change states and irreversible logic. Possible Fixes Possible Fixes Using Reversible Computing Logic Only represents minor gains of about 1-2 orders of magnitude Only represents minor gains of about 1-2 orders of magnitude Using New Logic Alternatives Spintronics Spintronics Phase Chase Logic Devices Phase Chase Logic Devices Interference devices Interference devices Optical Switches Optical Switches

6. Silicon Transistors The last 40 years of silicon transistor technology has been achieved with more or less the same techniques Metal-Oxide Semiconductor (MOS) Transistors Metal-Oxide Semiconductor (MOS) Transistors Complimentary MOS (CMOS) circuits to design logic gates Complimentary MOS (CMOS) circuits to design logic gates Materials: Si, SiO2, Al, Si3N4, TiSi2, Tin, W Materials: Si, SiO2, Al, Si3N4, TiSi2, Tin, W

7. Moore’s Law A new generation of technology is produced every 2-3 years Each new generation has: Twice the number of transistors Twice the number of transistors Increased performance by 40% Increased performance by 40% Four times the memory capacity Four times the memory capacity Hi.

8. Moore’s Law Increased number of transistors: where does it come from? Shrinking lithography dimensions (scaling) Shrinking lithography dimensions (scaling) Increase in chip area (cheating!) Increase in chip area (cheating!) “Cleverness” in design “Cleverness” in design With practical limits on chip area and the general unpredictability of “cleverness,” scaling is the most important aspect of Moore’s Law It is estimated that current technology will progress for another 10- 15 years before a new “breakthrough” is required

9. Limits of Scaling Physical Gate Oxide Thickness Max Silicide/Si Contact Resistivity Source/Drain Extension Sheet Resistance S/D Extension Junction Depth

10. Oxide Gate Thickness Present Day SiO 2 gate oxide SiO 2 gate oxide Has a low k Has a low k Makes near perfect electrical interface with Si Makes near perfect electrical interface with Si Effectively used up to 1.2nm thickness Effectively used up to 1.2nm thickness

11. Oxide Gate Thickness Problems Although most properties of the device have been scaled at similar rates the gate voltage has not. To compensate for this, the electric field across the capacitor increases. Although most properties of the device have been scaled at similar rates the gate voltage has not. To compensate for this, the electric field across the capacitor increases. At about 1nm, the thickness and large electric field causes a large leakage current do to electron tunneling At about 1nm, the thickness and large electric field causes a large leakage current do to electron tunneling

12. Oxide Gate Thickness Possible Solutions Strained Silicon Strained Silicon Used today in 90nm technology Allows greater mobility in channel thus lowering the leakage current High k dielectric High k dielectric High k allows for larger thickness while keeping the same capacitance Difficult to apply to silicon base without increasing scattering in channel

13. Shallow Junctions In MOSFET technology, the current drive limited by the channel resistance As MOSFETS get smaller parasitic resistances are no longer comparatively small To reduce these resistances doping is increased Doping is only feasible till electrical solubility limits are reached

15. Wire Restrictions While not directly related to silicon technology, wires represent a fundamental problem in miniaturization of circuits As transistors continue to shrink, wires and interconnect do not shrink at a similar pace As transistors continue to shrink, wires and interconnect do not shrink at a similar pace However, more and more wiring is needed to connect the increased number of transistors However, more and more wiring is needed to connect the increased number of transistors

16. Getting around Wire Limits Use fewer wires! Integrated circuits reduces the need for wiring Integrated circuits reduces the need for wiring Decreasing width of wiring Layering wires on top of each other

17. Problems with Decreasing Width Increases resistance per unit length Smaller cross-sectional area means increased resistance per unit length Smaller cross-sectional area means increased resistance per unit length Capacitance inversely increased, leading to constant RC times Capacitance inversely increased, leading to constant RC times As circuit speed increases, this leads to transmission delays limited by RC times rather than velocity of Electromagnetic waves As circuit speed increases, this leads to transmission delays limited by RC times rather than velocity of Electromagnetic waves

18. Problem with Longer Wiring Requires layering to separate each trace Leads to higher production costs Result: Production limits are sometimes restricted by monetary barriers, not technological limitations

19. Problems with Current Density Current density increase as cross-sectional area of the wire decreases Current density is limited by electromigration, the movement of atoms by electric currents Corrected, in part, by copper wiring Open Circuit FailureShort Circuit Failure

20. Current Density A numerical analysis: Electron density of copper Fermi speed, Ef = 7 eV Conductivity of copper at 20°C Mean free path of an electron Resistance, given diameter 1mm and length 1m Current density, given 1 volt Drift velocity More reasonable: 3A current yields 382 A/m^2 and a drift velocity of 0.00028 m/s

21. “Wire-Limited Chip” Concept Assumptions: the area needed for wiring dominates the area of the chip Each component has area a The component separation is a^0.5 Average length of the wire channels that must provided per component is ma^0.5, where m is the length in component pitches needed to run the wire Minimum distance between wires is W K is the number of layers Ka = m (a)^0.5 W A = (mW/K)^2