1. Pseudo-Random Pattern Generator Design for Column ‑ Matching BIST Petr Fišer Czech Technical University Dept. of Computer Science and Engineering

2. Outline Introduction Mixed-Mode Column-Matching BIST Weighted-Pattern testing & splitter ResultsConclusions

3. Introduction Discussion on the choice of the pseudorandom pattern generator (PRPG) in connection with Column-Matching BIST design method Target: low area overhead of both the PRPG and other BIST logic

4. Column-Matching BIST Pseudorandom patterns are generated by PRPG and then modified by a combinational logic into deterministic ones (by output decoder) For test-per-clock, patterns are applied in parallel

5. Standard Mixed-Mode Column-Matching BIST Combination of pseudorandom and deterministic testing (like bit- fixing, bit-flipping). Difference: these phases are disjoint The pseudorandom phase is run first, and then deterministic test is generated for undetected faults 100% fault coverage assumed

6. PRPG Issues & Choices LFSR CA Sometimes better, but not much (see DSD’05) LFSR width is one problem to solve PRPG fault coverage is the second problem

7. PRPG Issues & Choices m-bit wide LFSR is needed, in the standard approach Usually, m goes to thousands => high PRPG area overhead

8. Solution 1 Weighted pattern testing (LFSR outputs are AND-ed or OR-ed, to obtain weighted outputs) + Shorter LFSR + Higher fault coverage - Weighting logic overhead

9. Solution 2 Splitter (LFSR outputs are distributed to m CUT inputs by branching them) + Shorter LFSR - Less fault coverage + No weighting logic overhead

10. One Remark to This Weighted Pattern Testing 100% fault coverage is not the aim here The aim is minimum area overhead  More sophisticated methods, like multiple weights, MPLFSR, GURT, etc., are not welcome here

11. Weighting Logic Effects

12. How to Compute Weights Weights are derived from test vectors detecting random pattern resistant faults (RPRFs) Question: How to find them? Several pseudorandom vectors are applied to the CUT (by fault simulation), undetected faults are RPRFs. Major question: How many vectors?

13. How to Compute Weights

14. Some Comparisons LFSR (r)methodw CM time [s]GEs 233standard-2196061153.5 2333-w216264.59601415 2335-w4062261711566.5 50splitter-323475677.5 503-w219248.5427629.5 c2670 ISCAS benchmark circuit 233 inputs

15. Scaling Down the LFSR size LFSR (r)methodwCMtime [s]GEs 700standard-172.547202975 7003-w51840.52453361 2003-w36563.56531231 503-w365103.52835671 453-w365145.53423693 403-w365640.5294341288 303-w365--- s13207.1 ISCAS benchmark circuit 700 inputs

16. Conclusions Two (simple) PRPG design methods have been investigated: weighted pattern testing and splitting the LFSR outputs Primarily targeted to lower the area overhead Seems to be simple, but…

17. Here are the Buts… Weighted pattern testing works well. OK. But how many vectors should be simulated to obtain RPRFs to compute the weights? Numerous experiments have been performed, every benchmark circuit behaves differently

18. Here are the Buts… How many weights then? No weights, no weighting logic. More decoder logics. Too much weights, too much weighting logics. Less Decoder logics. Numerous experiments have been performed. No clue, unless the final result is computed

19. Here are the Buts… The LFSR width can be scaled. OK. But to what extent? Numerous experiments have been performed. No clue, unless the final result is computed

20. One Last Conclusion Lots to think about…