1. 08/08/12 www.eej.ulster.ac.uk/~ian/modules/COM181/files 1 COM181 Computer Hardware Lecture 4: The MIPs CPU Ian McCrumRoom 5B18, Tel: 90 366364 voice mail on 6 th ring Email: IJ.McCrum@Ulster.ac.uk Web site: http://www.eej.ulst.ac.ukIJ.McCrum@Ulster.ac.ukhttp://www.eej.ulst.ac.uk "Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, © 2008.” This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. Also drawn from the work of Mary Jane Irwin ( www.cse.psu.edu/~mji )www.cse.psu.edu/~mji

2. 25/05/12 www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 2 PCSrc Read Address Instruction Memory Add PC 4 0 1 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 1632 ALU 1 0 Shift left 2 Add Data Memory Address Write Data Read Data 1 0 IF/ID Sign Extend ID/EX EX/MEM MEM/WB Control 0 1 ALU cntrl Branch Forward Unit IF/ID.RegisterRs IF/ID.RegisterRt EX/MEM.RegisterRd MEM/WB.RegisterRd The MIPs CPU is described in the textbook, note how the diagram below relates to lecture 3

3. 25/05/12www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 3 Often you must deal with the management of complexity, and use abstraction and partition to reduce systems to sizes that the human brain can cope with... When programming a MIPs CPU it is enough to maintain a “Programmer’s Model” of the CPU. The CPU is designed as a RISC (Reduced Instruction Set Computer) machine, this suits implementing the hardware but not necessarily suits humans programming it! Software tools help A RISC machine has a fixed length instruction (32 bits in the simple MIPs) A RISC machine has a limited number of addressing modes A RISC machine has a limited number of operations (small instrucution set) A RISC machine has, typically, a register bank and uses load/store instructions (only) to access main memory.

4. 25/05/12www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 4 MIPs machines have three types of Instruction; R-type for arithmetic instructions – using Registers, I-type where the number needed is available immediately and J-type for conditional/control, jumps etc (there are also a few others...) Example of some MIPS assembly language arithmetic statements add$t0, $s1, $s2 sub$t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands destination  source1 op source2 Operand order is fixed (the destination is specified first) The operands are contained in the datapath’s register file ( $t0, $s1, $s2 ) The registers above have been given symbolic names, the actual numbered registers Run from $0 to $31. We use software to convert the statements above to a 32 bit instruction. The ASSEMBLER program can also convert symbols into numbers

5. MIPS Register File Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file  Thirty-two 32-bit registers Two read ports One write port Registers are  Fast Smaller is faster & Make the common case fast  Easy for a compiler to use e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order  Improves code density Since register are named with fewer bits than a memory location Register addresses are indicated by using $

6. MIPS Register File Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file  Thirty-two 32-bit registers Two read ports One write port Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations 32 5 5 5  Registers are l Fast -Smaller is faster & Make the common case fast l Easy for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order l Improves code density -Since register are named with fewer bits than a memory location  Register addresses are indicated by using $ 2 5 =

7. 0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

8. Registers vs. Memory Arithmetic instructions operands must be in registers  only thirty-two registers are provided Compiler associates variables with registers What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output Network

9. Registers vs. Memory Arithmetic instructions operands must be in registers  only thirty-two registers are provided Compiler associates variables with registers Processor Control Datapath Memory Devices Input Output Network What about programs with lots of variables?

10. Memory is a large, single-dimensional array An address acts as the index into the memory array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data 1 101 10

11. Memory is a large, single-dimensional array An address acts as the index into the memory array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data 32 2 32 Bytes (4 GB)  2 30 Words (1 GW) = 4 Bytes = 1 Word 1 101 10 0 4 8 The data stored in the memory The word address of the data

12. MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 24 10 ) lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory The data transfer instruction must specify  where in memory to read from (load) or write to (store) – memory address  where in the register file to write to (load) or read from (store) – register destination (source) The memory address is formed by summing the constant portion of the instruction and the contents of the second register Accessing Memory

13. MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 24 10 ) lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory The data transfer instruction must specify  where in memory to read from (load) or write to (store) – memory address  where in the register file to write to (load) or read from (store) – register destination (source) The memory address is formed by summing the constant portion of the instruction and the contents of the second register Accessing Memory 28 32

14. Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0]

15. Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0] lw$t0, 8($s3) sub$t0, $t0, $s2 sw$t0, 32($s3)

16. Compiling with a Variable Array Index Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i $s4 $s4 +4 $s4 +8 $s4 +12... A[2] A[3]... A[1] A[0]

17. Compiling with a Variable Array Index Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i $s4 $s4 +4 $s4 +8 $s4 +12... A[2] A[3]... A[1] A[0] add$t1, $t1, $s4#addr of A[i] now in $t1 lw$t0, 0($t1) sub$s2, $t0, $s1

18. Small constants are used quite frequently (50% of operands in many common programs) e.g., A = A + 5; B = B + 1; C = C - 18; Solutions? Why not?  Put “typical constants” in memory and load them  Create hard-wired registers (like $zero) for constants like 1, 2, 4, 10, … Dealing with Constants  How do we make this work?  How do we Make the common case fast !

19. Include constants inside arithmetic instructions  Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself) MIPS immediate instructions addi$s3, $s3, 4#$s3 = $s3 + 4 Constant (or Immediate) Operands There is no subi instruction, can you guess why not?

20. MIPS Instructions, so far CategoryInstrExampleMeaning Arithmeticaddadd $s1, $s2, $s3$s1 = $s2 + $s3 subtractsub $s1, $s2, $s3$s1 = $s2 - $s3 add immediate addi $s1, $s2, 4$s1 = $s2 + 4 Data transfer load wordlw $s1, 32($s2)$s1 = Memory($s2+32) store wordsw $s1, 32($s2)Memory($s2+32) = $s1

21. Instructions, like registers and words of data, are also 32 bits long  Example: add $t0, $s1, $s2 registers have numbers $t0=$8,$s1=$17,$s2=$18 Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000

22. Instructions, like registers and words of data, are also 32 bits long  Example: add $t0, $s1, $s2 registers have numbers $t0=$8,$s1=$17,$s2=$18 Instruction Format: Machine Language - Arithmetic Instruction op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000 Can you guess what the field names stand for?

23. MIPS Instruction Fields op rs rt rd shamt funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits

24. MIPS Instruction Fields op rs rt rd shamt funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amoun t (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field

25. Consider the load-word and store-word instr’s  What would the regularity principle have us do? But... Good design demands compromise Introduce a new type of instruction format  I-type for data transfer instructions (previous format was R-type for register) Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number 23 hex 18 8 24 100011 10010 01000 0000000000011000

26. Consider the load-word and store-word instr’s  What would the regularity principle have us do? But... Good design demands compromise Introduce a new type of instruction format  I-type for data transfer instructions (previous format was R-type for register) Example: lw $t0, 24($s2) Machine Language - Load Instruction op rs rt 16 bit number 23 hex 18 8 24 100011 10010 01000 0000000000011000 Where's the compromise?

27. Memory Address Location Example: lw $t0, 24($s2) Memory dataword address (hex) 0x00000000 0x00000004 0x00000008 0x0000000c 0xf f f f f f f f $s2 0x12004094 0x00000002 24 10 + $s2 = Note that the offset can be positive or negative

28. Memory Address Location Example: lw $t0, 24($s2) Memory dataword address (hex) 0x00000000 0x00000004 0x00000008 0x0000000c 0xf f f f f f f f $s2 0x12004094 0x00000002 24 10 + $s2 = Note that the offset can be positive or negative... 1001 0100 +... 0001 1000... 1010 1100 = 0x120040ac $t0

29. Example: sw $t0, 24($s2) A 16-bit offset means access is limited to memory locations within a range of +2 13 -1 to -2 13 (~8,192) words (+2 15 -1 to - 2 15 (~32,768) bytes) of the address in the base register $s2  2’s complement (1 sign bit + 15 magnitude bits) Machine Language - Store Instruction op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000

30. Example: sw $t0, 24($s2) A 16-bit offset means access is limited to memory locations within a range of +2 13 -1 to -2 13 (~8,192) words (+2 15 -1 to -2 15 (~32,768) bytes) of the address in the base register $s2  2’s complement (1 sign bit + 15 magnitude bits) Machine Language - Store Instruction op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000

31. What instruction format is used for the addi ? addi$s3, $s3, 4#$s3 = $s3 + 4 Machine format: Machine Language – Immediate Instructions

32. What instruction format is used for the addi ? addi$s3, $s3, 4#$s3 = $s3 + 4 Machine format: Machine Language – Immediate Instructions op rs rt 16 bit immediate I format 8 19 19 4  The constant is kept inside the instruction itself! l So must use the I format – Immediate format l Limits immediate values to the range +2 15 –1 to -2 15

33. Instruction Format Encoding Can reduce the complexity with multiple formats by keeping them as similar as possible  First three fields are the same in R-type and I-type Each format has a distinct set of values in the op field InstrFrmtoprsrtrdshamtfunctaddress add R0reg 032 ten NA sub R0reg 034 ten NA addi I8 ten reg NA constant lw I35 ten reg NA address sw I43 ten reg NA address

34. Assembling Code Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS object code for these three instructions (decimal is fine) lw sw sub

35. Assembling Code Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8] Assemble the MIPS object code for these three instructions (decimal is fine) 35 lw 198843 sw 198320 sub 8188034

36. Review: MIPS Instructions, so far CategoryInstrOp Code ExampleMeaning Arithmetic (R format) add0 & 32 add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 & 34 sub $s1, $s2, $s3$s1 = $s2 - $s3 Arithmetic (I format) add immediate 8addi $s1, $s2, 4$s1 = $s2 + 4 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1

37. MIPS Operand Addressing Modes Summary Register addressing – operand is in a register  Base (displacement) addressing – operand’s address in memory is the sum of a register and a 16-bit constant contained within the instruction  Immediate addressing – operand is a 16-bit constant contained within the instruction 1. Register addressing op rs rt rd funct Register word operand op rs rt offset 2. Base addressing base register Memory word or byte operand 3. Immediate addressing op rs rt operand

38. MIPS Instruction Addressing Modes Summary  PC-relative addressing – instruction’s address in memory is the sum of the PC and a 16-bit constant contained within the instruction  Pseudo-direct addressing – instruction’s address in memory is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC 4. PC-relative addressing op rs rt offset Program Counter (PC) Memory branch destination instruction 5. Pseudo-direct addressing op jump address Program Counter (PC) Memory jump destination instruction||

39. Review: MIPS Instructions, so far CategoryInstrOpCExampleMeaning Arithmetic (R & I format) add0 & 20add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 & 22sub $s1, $s2, $s3$s1 = $s2 - $s3 add immediate8addi $s1, $s2, 4$s1 = $s2 + 4 shift left logical0 & 00sll $s1, $s2, 4$s1 = $s2 << 4 shift right logical0 & 02srl $s1, $s2, 4$s1 = $s2 >> 4 (fill with zeros) shift right arithmetic 0 & 03sra $s1, $s2, 4$s1 = $s2 >> 4 (fill with sign bit) and0 & 24and $s1, $s2, $s3$s1 = $s2 & $s3 or0 & 25or $s1, $s2, $s3$s1 = $s2 | $s3 nor0 & 27nor $s1, $s2, $s3$s1 = not ($s2 | $s3) and immediatecand $s1, $s2, ff00$s1 = $s2 & 0xff00 or immediatedor $s1, $s2, ff00$s1 = $s2 | 0xff00 load upper immediate flui $s1, 0xffff$s1 = 0xffff0000

40. Review: MIPS Instructions, so far CategoryInstrOpCExampleMeaning Data transfer (I format) load word23lw $s1, 100($s2)$s1 = Memory($s2+100) store word2bsw $s1, 100($s2)Memory($s2+100) = $s1 load byte20lb $s1, 101($s2)$s1 = Memory($s2+101) store byte28sb $s1, 101($s2)Memory($s2+101) = $s1 load half21lh $s1, 101($s2)$s1 = Memory($s2+102) store half29sh $s1, 101($s2)Memory($s2+102) = $s1 Cond. branch (I & R format) br on equal4beq $s1, $s2, Lif ($s1==$s2) go to L br on not equal5bne $s1, $s2, Lif ($s1 !=$s2) go to L set on less than immediate aslti $s1, $s2, 100if ($s2<100) $s1=1; else $s1=0 set on less than0 & 2aslt $s1, $s2, $s3if ($s2<$s3) $s1=1; else $s1=0 Uncond. jump jump2j 2500go to 10000 jump register0 & 08jr $t1go to $t1 jump and link3jal 2500go to 10000; $ra=PC+4

41. Review: MIPS R3000 ISA Instruction Categories  Load/Store  Computational  Jump and Branch  Floating Point coprocessor  Memory Management  Special 3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO OPrs rt rdshamtfunct OPrs rt 16 bit number OP 26 bit jump target Registers R format I format 6 bits5 bits 6 bits J format

42. RISC Design Principles Review Simplicity favors regularity  fixed size instructions – 32-bits  small number of instruction formats Smaller is faster  limited instruction set  limited number of registers in register file  limited number of addressing modes Good design demands good compromises  three instruction formats Make the common case fast  arithmetic operands from the register file (load-store machine)  allow instructions to contain immediate operands

43. The Code Translation Hierarchy C program compiler assembly code

44. Compiler Transforms the C program into an assembly language program Advantages of high-level languages  many fewer lines of code  easier to understand and debug  … Today’s optimizing compilers can produce assembly code nearly as good as an assembly language programming expert and often better for large programs  smaller code size, faster execution

45. The Code Translation Hierarchy C program compiler assembly code assembler object code

46. 25/05/12www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 46 Does a syntactic check of the code (i.e., did you type it in correctly) and then transforms the symbolic assembler code into object (machine) code Advantages of assembler  much easier than remembering instr’s binary codes  can use labels for addresses – and let the assembler do the arithmetic  can use pseudo-instructions e.g., “move $t0, $t1” exists only in assembler (would be implemented using “add $t0,$t1,$zero”) When considering performance, you should count instructions executed, not code size Assembler

47. 25/05/12www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 47 1. Builds a symbol table which holds the symbolic names (labels) and their corresponding addresses  A label is local if it is used only within the file where its defined. Labels are local by default.  A label is external (global) if it refers to code or data in another file or if it is referenced from another file. Global labels must be explicitly declared global (e.g.,.globl main ) 2. Translates each assembly language statement into object (machine) code by “assembling” the numeric equivalents of the opcodes, register specifiers, shift amounts, and jump/branch targets/offsets The Two Main Tasks of the Assembler

48. MIPS (spim) Memory Allocation Memory 2 30 words 0000 f f f f f f f c Text Segment Reserved Static data Mem Map I/O 0040 0000 1000 0000 1000 8000 7f f f f f fc Stack Dynamic data $sp $gp PC Kernel Code & Data

49. Other Tasks of the Assembler Converts pseudo-instr’s to legal assembly code  register $at is reserved for the assembler to do this Converts branches to far away locations into a branch followed by a jump Converts instructions with large immediates into a lui followed by an ori Converts numbers specified in decimal and hexidecimal into their binary equivalents and characters into their ASCII equivalents Deals with data layout directives (e.g.,.asciiz ) Expands macros (frequently used sequences of instructions)

50. Typical Object File Pieces Object file header: size and position of the following pieces of the file Text (code) segment (.text ) : assembled object (machine) code Data segment (.data ) : data accompanying the code  static data - allocated throughout the program  dynamic data - grows and shrinks as needed Relocation information: identifies instructions (data) that use (are located at) absolute addresses – not relative to a register (including the PC)  on MIPS only j, jal, and some loads and stores (e.g., lw $t1, 100($zero) ) use absolute addresses Symbol table: global labels with their addresses (if defined in this code segment) or without (if defined external to this code segment) Debugging information

51. An Example.data.align0 str:.asciiz "The answer is " cr:.asciiz "\n".text.align2.globlmain.globlprintf main:ori$2, $0, 5 syscall move $8, $2 loop:beq$8, $9, done blt$8, $9, brnc sub$8, $8, $9 jloop brnc:sub$9, $9, $8 jloop done:jalprintf Gbl?SymbolAddress str 1000 0000 cr 1000 000b yes main 0040 0000 loop 0040 000c brnc 0040 001c done 0040 0024 yes printf ???? Relocation Info AddressData/Instr 1000 0000 str 1000 000b cr 0040 0018 j loop 0040 0020 j loop 0040 0024 jal printf

52. The Code Translation Hierarchy C program compiler assembly code assembler object code library routines executable linker machine code main text segment printf text segment

53. Linker Takes all of the independently assembled code segments and “stitches” (links) them together  Faster to recompile and reassemble a patched segment, than it is to recompile and reassemble the entire program 1. Decides on memory allocation pattern for the code and data segments of each module  Remember, modules were assembled in isolation so each has assumed its code’s starting location is 0x0040 0000 and its static data starting location is 0x1000 0000 2. Relocates absolute addresses to reflect the new starting location of the code segment and its data segment 3. Uses the symbol tables information to resolve all remaining undefined labels  branches, jumps, and data addresses to/in external modules Linker produces an executable file

54. Linker Code Schematic printf:. main:. jal ???? call, printf Linker Object file C library Relocation info main:. jal printf printf:. Executable file

55. Linking Two Object Files Hdr Txtseg Dseg Reloc Smtbl Dbg File 1 Hdr Txtseg Dseg Reloc Smtbl Dbg File 2 + Executable Hdr Txtseg Dseg Reloc

56. The Code Translation Hierarchy C program compiler assembly code assembler object code library routines executable linkerloader memory machine code

57. Loader Loads (copies) the executable code now stored on disk into memory at the starting address specified by the operating system Copies the parameters (if any) to the main routine onto the stack Initializes the machine registers and sets the stack pointer to the first free location (0x7fff fffc) Jumps to a start-up routine (at PC addr 0x0040 0000 on xspim) that copies the parameters into the argument registers and then calls the main routine of the program with a jal main

58. Dynamically Linked Libraries Statically linking libraries mean that the library becomes part of the executable code  It loads the whole library even if only a small part is used (e.g., standard C library is 2.5 MB)  What if a new version of the library is released ? (Lazy) dynamically linked libraries (DLL) – library routines are not linked and loaded until a routine is called during execution  The first time the library routine called, a dynamic linker-loader must find the desired routine, remap it, and “link” it to the calling routine (see book for more details)  DLLs require extra space for dynamic linking information, but do not require the whole library to be copied or linked

59. 25/05/12www.eej.ulster.ac.uk/~ian/modules/COM181/fi les 59