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Course Wrap-Up Miodrag Bolic CEG4136
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What was covered Interconnection network topologies and performance Shared-memory architectures Message passing architectures Scheduling Multicores and networks on chip Cloud computing Elements of system-on-chip design in Labs and sometimes during lectures Basic elements of parallel programming
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What was not covered Parallel programming Operating systems Advanced manycore architectures
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Final Format Duration: 3 hours Format: –1 theoretical problem –4 problems with multiple parts
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Final Format Closed book, closed notes exam. No cheat sheet Only material cover in the class, DGDs, assignments and labs will be on the exam.
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Complaining You can come to see the exam on –Fri (Dec 23rd) 13:00-14:00 To complain: you will fill the form and I will notify you about the decision.
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Things to Review Assignments Lecture notes Quizzes from 2005, 2006 and 2007
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Format 1.Theoretical question 2.Interconnection networks 3.Message passing and scheduling 4 Shared memory systems 5 Advanced architectures or scheduling
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Example of the theoretical question for final Type of questions: Compare Define and explain What to study: Everything
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Dynamic Interconnection Networks Properties –Network latency –Hardware complexity –Blocking/Nonblocking Switches –Permutations and legitimate states Multistage Interconnection networks –Omega network: »topology, »number of switches, stages and permutations, »routing protocol Crossbar
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Static Interconnection Networks Network properties –Node degree d –Diameter D –Bisection width Complete Star Tree Linear array Ring Mesh Torus Hypercube –routing protocol k-ary n-cubes To prepare for dynamic and static interconnection networks use –slides, –assignment and
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Message passing Message Passing Properties Store-and-forward routing Wormhole routing Virtual channels Deterministic routing algorithms Deadlocks
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Scheduling Dependence graph Scheduling without considering communication –Scheduling inforest/outforest task graphs Heuristic algorithms –Communication Delay versus Parallelism –Clustering –Node duplication
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Shared Memory Systems Cache coherence policies –Snooping protocols –Directory protocols
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Parallel programing Parallel addition and matrix multiplication on shared memory and message passing systems Again – you will be required to modify the given program
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Performance Amdahl law Speedup, Efficiency Parallelism profile, average parallelism, MIPS Scalability Understanding of performance of the program for parallel addition Classification of parallel processing systems
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Embedded multicores Review terminology –Symmetric and Asymetric processing –Virtualization and hypervisor –Cache stashing –Run to completion –Posix and OpenMP Example of router implementation using processor cores
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Cache coherence for manycores Coherence Bandwidth Requirements Broadcast vs. Directory Protocols Read hit and read miss procedure for: –Private L2 caches –Shared L2 caches
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Router design for manycores Architecture of the virtual channel router Pipeline stages –Lookahead routing Buffer Organization Switch organization Arbiters and allocators –Round-robin arbiter
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Cloud computing Terminology Services Advantages Comparison with grid and high-performance computing
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