1. Page - 1 The Leading Provider of EDA Software & Technologies for the Physical Implementation of Structured ASICs

2. Page - 2 11/21/2000 www.ViASIC.com ViASIC, Inc. Early-stage EDA software company Located in Research Triangle Park, NC Founded 1999 Growing, profitable, debt-free, low burn rate ViaPath/ViaMask products first announced in May 2003 Four customers since announcement Two patents on ViaPath/ViaMask granted –6,693,454 & 6,580,289 –more on the way Experienced management team Closed investment round in late 2003

3. Page - 3 11/21/2000 www.ViASIC.com Why Use A Structured ASIC Fabric

4. Page - 4 11/21/2000 www.ViASIC.com interconnect

5. Page - 5 11/21/2000 www.ViASIC.com Logic Cell Schematic

6. Page - 6 11/21/2000 www.ViASIC.com memory architecture Stretch custom RAM along word lines: Increase size of word line driver Keeps bit lines and therefore SA size the same Patent 6,693,454 Traditional Ram vs. Distributed RAM

7. Page - 7 11/21/2000 www.ViASIC.com ViaMask Nomenclature for TSMC/ST 0.13 Micron 6ML

8. Page - 8 11/21/2000 www.ViASIC.com Available Libraries Include: TSMC 0.13 6ML ST 0.13 6ML TSMC 0.13 8ML AMS 0.35 4ML IBM 0.13 6ML in development Customization of fabric is available

9. Page - 9 11/21/2000 www.ViASIC.com Features  Simultaneously available embedded RAM  Typically routes 100% utilized designs  Available via configurable ROM  Programmable partition power-down  Unlimited clock domains  Fits traditional design flows  Standard test flow  Generates files for LVS/LEC  Diodes for antenna repair

10. Page - 10 11/21/2000 www.ViASIC.com The Best Structured ASIC Single mask SOC or full-chip RAM & logic Excellent density & performance

11. Page - 11 11/21/2000 www.ViASIC.com Vs. Other SA Architectures

12. Page - 12 11/21/2000 www.ViASIC.com DFM Issues Phase-shift coloring compatible Repetitive structures can lead to yield improvements Redundant vias between in-line routing segments Uniform metal Very wide power busses Via-configured power-down of unused logic

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14. Page - 14 11/21/2000 www.ViASIC.com Features  Timing driven placement  Capacitance driven global routing  Signal Integrity driven detailed routing  Tie off of unused inputs  Built in RAM generator  Support traditional test flow with scan-chain interface to Tetramax  Antenna violation detection and repair  Buffer insertion for timing resolution  Integrated clock routing  Routing turn minimization  Fast run times  Efficient runtime memory usage  Automatic selection of target footprint  Integrates easily into existing tool flows  Accurate delay simulation  TCL interface for low level control  Place & route an embedded block of an SoC or a full chip

15. Page - 15 11/21/2000 www.ViASIC.com ViaPath Treatment of SI Simpler problem, since post-detailed routing changes are easily done Cross-talk fixed post 3-D extraction Effective speedup of critical signals: –Buffering, duplication, and gate sizing –During global route –During detailed route –Incrementally, after 3-D extraction True 3-D extraction of parasitics White paper available

16. Page - 16 11/21/2000 www.ViASIC.com Sample Design A Process: AMS 0.35 4ML Application: Fabric for Triad Semi (fabless structured ASIC manufacturer) Footprint: 3x8 tiles Die Size: 2.37mm x 2.98mm 7.06 mm 2 Sample design in this footprint was 35K gates & 3 memories ViaPath runtime of 45 seconds with memory usage of 152MB (on 1.8 GHz Opteron)

17. Page - 17 11/21/2000 www.ViASIC.com Sample Design B Process: TSMC 0.13 6ML Application: Configurable Embedded Block of SOC Footprint: 10x13 tiles Die Size: 2.76mm x 3.71mm 10.24 mm 2 w/power ring Initial Design for this footprint was 600K gates & 20 memories ViaPath runtime of 2.5 hrs with memory usage of 2.035 GB (on 1.8 GHz Opteron)

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19. Page - 19 11/21/2000 www.ViASIC.com For Microcontroller Two ViaMask fabrics –0.25 4 ML in 5-50k gate footprints –0.13 6 ML in 50-200k gate footprints Embedded Area could be –Single port SRAM –cache –Eprom Pick a single-footprint launch to cover ViASIC’s cost, Freescale can upgrade once proven.

20. Page - 20 11/21/2000 www.ViASIC.com Contact Info William Westhead France +33 5 55 09 60 49 westhead@libertysurf.fr * Max Lloyd, CEO 919-767-6941 max@viasic.com

21. Page - 21 11/21/2000 www.ViASIC.com The Time Is Now Sample Roll-out Plan

22. Page - 22 11/21/2000 www.ViASIC.com Virage ASAP Metal Programmed Library Each respin requires standard-cell like routing to be rerun with corresponding closures of timing, signal integrity, and power. To approach ViaMask density Virage needs at least 6 masks (Via1 thru Metal 4). ViaMask uses only one mask, Via3. Memory in the Virage architecture is not reconfigurable. Customer should benchmark two netlists (designs) into same footprint for real world understanding of Virage density.

23. Page - 23 11/21/2000 www.ViASIC.com Semiconductor’s Fastest Growing Segment “Worldwide merchant market dollar shipments of structured ASIC products are forecast to grow from the $5.2 million reached [in 2002], to $460.3 million by 2007. This will translate to a forecast Compound Annual Growth Rate (CAGR), over the 2002 to 2007 forecast period, of 145%.”

24. Page - 24 11/21/2000 www.ViASIC.com Structured ASICs - Solution –mask costs –time to market –yields –advanced rules –risk

25. Page - 25 11/21/2000 www.ViASIC.com ST 0.13 6ML cell

26. Page - 26 11/21/2000 www.ViASIC.com Increasing mask costs are limiting electronic innovation One respin pays for a copy of ViaPath ViASIC solutions enable new markets

27. Page - 27 11/21/2000 www.ViASIC.com Details Inputs Synthesized netlist in Verilog or VHDL Physical design data in.lib, LEF/DEF Timing constraints in SDC Outputs Via photomask in GDSII Path delay data in SDF Auto pin assignment in TCL Scan chain reordering interface to Tetramax Print and plot data in Postscript Verilog for LVS & formal verification Supported Platforms RedHat 32-bit Linux on AMD & Intel processors 64 bit Linux and Solaris also available

28. Page - 28 11/21/2000 www.ViASIC.com ViaPath Features, Release Plan 2004.4 Spice Translation/Synthesis for Analog P&R Skew of MUX balancing for additional timing resources Configurable power, power estimation Signal integrity driven routing (wire swapping/avoidance, shielding) Path highlighting display Complete timing driven (additional SDC support) Timing modeling, reporting (include clock skew report) Enable File/Print of Postscript Image 2005.2 Fly line connectivity display Scan chain link to Tetramax Non-rectangular footprint support Hierarchical design support, nested footprint support LEF macro input

29. Page - 29 11/21/2000 www.ViASIC.com Current Products ViaMask –One-mask structured ASIC libraries –Announced May 2003 ViaPath –Physical design tool for one-mask structured ASICs and VPGA –Announced May 2003 VRoute –Routing engine for standard-cell and metal programmed structured ASICs –First tape-out March 2004, demo’d at DAC 2004 –To be released