1. Automatic Communication Refinement for System Level Design Samar Abdi, Dongwan Shin and Daniel Gajski Center for Embedded Computer Systems, UC Irvine http://www.cecs.uci.edu

2. Outline Main Idea Related work Introductory example Communication refinement Experimental results Impact on SLD

3. Possible Design Methodology Specification Model Transaction model Communication model Implementation model Software compilation Interface synthesis Hardware synthesis Refinement Designer Decisions Evaluate Refinement Evaluate ~6.5K LOC ~8K LOC ~9K LOC ~15K LOC

4. Motivation Rewriting system models is painful –Time consuming –Error prone Goal : Automatic model rewriting Extra benefits : –Speedy Design space exploration –Choose a good communication architecture

5. Related Work CoWare (Symphony, DAC 1996) –Rendezvous point to point communication with RPC TIMA (A. Jerraya et al. DAC 2001) –Interface library for parameterized components –Communication using FIFO channels SystemC Co-centric Studio ( http://www.synopsys.com/products/cocentric_studio) –Modeling and Simulation SCE (http://www.cecs.uci.edu/~cad/sce.html) –Synthesis –Refinement –Evaluation

6. Decisions and Refinement Transaction level Model –Tasks divided amongst components. –Point to point data transaction channels. transaction channels. Generate pin-accurate communication model from transaction level model Communication Model –System Buses –Bus Interfaces –Communication structures ? SWHW2 TC1TC2TC3 HW1 Arbiter SWHW2HW1 IC Designer Decisions

7. Communication Refinement Protocol Library SWHW1HW2 SWHW1HW2 TC1TC3TC2 Arbiter IC Designer Decisions Bus Selection Channel Partitioning Interrupt controller type Arbitration policy Transaction Level Model Communication Model Bus 1 (protocol 1) Bus 2 (protocol 2)

8. Transaction Channel Definition Two way blocking communication between components Complex data structures Deterministic behavior Relatively independent DATA Send Recv Write DATARead DATA ready wait ack wait TC

9. Refinement Example SW (Master) Send (v) HW (Slave) v = Recv( ) ch Data Simplification Bit-stream gen. Write words Bus Master IF Data Regeneration Bit-stream gen. Read words Bus Slave IF System Bus Wires Interrupt Added during communication refinement Interrupt Handler Ready Flag Application Layer Application Layer

10. Communication Style for 2 Statically scheduled components Master ComponentSlave Component Application LayerInterrupt Handler Application Layer I1 I2 S3 S2 S1 A1 A2 SlaveReady == FALSE SlaveReady == TRUE Bus Transfer SlaveReady = FALSE Interrupt == 0 Interrupt == 1 SlaveReady = TRUE Notify Interrupt BusAddress != SlaveAddress BusAddress == SlaveAddress Bus Transfer

11. Communication Style for Dynamically scheduled master with multiple slaves Master ComponentSlave Component Application Layer (for variable vi) Interrupt HandlerApplication Layer I1 I2 S3 S2 S1 A1 A2 SlaveReady [ i ] == FALSE SlaveReady [ i ] == TRUE Bus Transfer SlaveReady[i] = FALSE Interrupt == 0 Interrupt == 1 SlaveReady[ i ] = TRUE Notify Interrupt BusAddress != SlaveAddress BusAddress == SlaveAddress Bus Transfer Reserve IOPort Release IOPort I2 i = ReadSlaveID()

12. For Each bus with numMasters > 1 –Instantiate Arbiter –Make req/gnt port connections For each master with numSlaves > InterruptPorts –Instantiate Interrupt Controller –Make req/gnt port connections For each application channel in master –CodeGen (wait SlaveReady) –If (dynamic scheduling) CodeGen (req Bus Access) –If (multiple masters) CodeGen (req Bus; wait gnt) For each application channel in slave –CodeGen (notify Interrupt) –If (multiple slaves) CodeGen (wait gnt) CodeGen (notify address) Depth first traversal over complex data structure For each Integral type –Convert to bit vector –Slices of data bus width Generate Code to write sliced words on data bus Complete Refinement Algorithm Derive Connectivity –Instantiate protocol channels Instantiate application channels Instantiate communication structures Slice data Add synchronization –Master –Slave –Interrupt Handler B1B2C1MS C2M/SS C3SM Bus Comp Transaction channel ch1ch2typesendrecv busB1/MB2/S App. Ch. A1(B1m)A2(B2s)

13. Productivity Gain SystemArchitecture Transaction model size (LOC)Comm. Model size (LOC)ModifiedLOCAutoRefineTimeManualRefineTime 1 DSP + 2 HW +1 DSPBus 112921258123920.480s ~240 h 1 DSP + 4 HW +1 DSPBus + 2 HSBus 2547028950199271.923s ~2000 h 2 DSP + 7 HW +2 DSPBus + 2 HSBus 2547037629213753.761s ~2140 h GSM Vocoder models used Experiments done on a 2 GHz Pentium 4 machine using SCE (System-on-Chip Environment) Manual refinement estimated at modifying 10 LOC/person-hr

14. Quality Analysis Vocoder Model (1 DSP, 1 HW, 1 DSPBus) –Transaction model size : 7992 LOC –Modified lines of code Manual refinement : 1141 LOC Automatic refinement : 1299 LOC ×Spurious application channel generation 2 application channels per transaction channel2 application channels per transaction channel optimized by identifying reusable application channelsoptimized by identifying reusable application channels Automatically generated code is more modular and understandable Automatically generated code is more modular and understandable

15. Conclusions Automatic generation of communication models High productivity gain Applicable to complex communication architectures Extensive exploration possible Automatically generated models are maintainable Improvements to refinement algorithm in the future Visit http://www.cecs.uci.edu/~cad/sce.html