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Accelerating Design Cycles Using Quartus II

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Presentation on theme: "Accelerating Design Cycles Using Quartus II"— Presentation transcript:

1 Accelerating Design Cycles Using Quartus II
SignalTap II Embedded Logic Analyzer

2 SignalTap II Agenda SignalTap II Overview & Features
Using SignalTap II Interface Advanced Triggering

3 SignalTap II ELA Captures the Logic State of FPGA Internal Signals Using a Defined Clock Signal Gives Designers Ability to Monitor Buried Signals Connects to Quartus II through FPGA JTAG Pins Captures Real-Time Data Up to 200 Mhz Is Available for Free Installed with Full Subscription or Web Edition Installed with Stand-Alone Programmer

4 SignalTap II Device Support
Stratix & Stratix II Stratix GX Cyclone & Cyclone II Excalibur Mercury APEX II APEX 20K/E/C

5 How Does It Work? Configure ELA
Download ELA into FPGA along with Design ELA Samples Internal Signals Quartus II Communicates with ELA through JTAG

6 ELA Resource Utilization
ELA Uses Device Resources for Implementation ALMs/LEs for ELA Megafunction & Routing Memory for Sample Storage LE Count Is a Function of the Number of Channels & Trigger Levels Memory Block Count Is a Function of Number of Channels & Sample Depth Selectable Trade-off Between Depth & Number of Channels 128K Sample Depth with 1024 Channels Is Not Practical – 32,768 M4K Blocks

7 Stratix/Cyclone Sample Resource Usage
Number of Channels Logic Elements Trigger Level 1 Trigger Level 2 Trigger Level 3 8 316 371 426 32 566 773 981 256 2900 4528 6156 Number of Channels M4Ks Based on Sample Depth 256 512 2K 8K 32K 8 < 1 1 4 16 64 32 2 128

8 Modes of Operation Three Different Configurations
Internal RAM ELA Configuration Debug Port ELA Configuration Hybrid Approach Provides Flexibility Based on Available Device Resources Memory Resources Are Limited Use Debug Port Configuration Pin Resources Are Limited Use Internal RAM Configuration

9 Internal RAM Configuration
Acquired Data Saved in Device Internal RAM Streamed Off-device through JTAG Port LEs Required to Implement ELA Core Logic ELA Core Logic Memory Signals From Internal Nodes JTAG Port To JTAG Connector

10 Debug Port Configuration
Acquired Data Routed to Unused Device I/O Pins Captured by External Logic Analyzer or Oscilloscope LEs Required to Implement ELA Core Logic I/O Pins Required for External Analysis Signals From Internal Nodes To Unused I/O Pins Signals to Debug Ports ELA Core Logic

11 Supported Download Cables
USB Blaster USB Port Cable ByteBlaster™ II Parallel Port Cable ByteBlasterMV™ Parallel Port MasterBlaster™ USB / Serial Port Cable

12 SignalTap II Key Features
Setup Data Triggering Data Capture Data Analysis

13 Setup Features Up to 1024 Data Channels
Data Triggering Data Capture Data Analysis Up to 1024 Data Channels Multiple Analyzers in One Device Supports Analysis of Multiple Clock Domains Each Analyzer Can Run Simultaneously Resource Usage Estimation Incrementally Routes New Signals

14 Data Triggering Features
Setup Data Triggering Data Capture Data Analysis Up to 10 Trigger Levels Per Channel Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes Defines a Sequential Pattern of Logic Conditions Each Trigger Level is Logically ANDED If (L1 & L2 ... & L10) == TRUE  Data Capture

15 Data Triggering Features (Cont.)
Setup Data Triggering Data Capture Data Analysis Three Main Trigger Positions Trigger Input Setup External Trigger to Trigger the Analyzer Trigger Output Signifies Trigger Event Occurred with SignalTap II Use One ELA’s Trigger Output as Trigger Input for Another TIME Old Samples New Samples trigger Samples Captured Data Triggering

16 Data Capture Features Up to 128K Samples Per Channel
Setup Data Triggering Data Capture Data Analysis Up to 128K Samples Per Channel Increases Chance of Catching Target Event Two Methods of Data Acquisition Circular Segmented Mnemonic Tables Create User-Defined Labels for Bit Sequences (Ex. State Machine)

17 Data Analysis Features
Setup Data Triggering Data Capture Data Analysis Data Export Save Real Time Data & Apply Data as Stimulus to Simulation Data Log Keep a a Log of Captured Data Compare Old Data Vs. New Data

18 SignalTap II Agenda SignalTap II Overview & Features
Using SignalTap II Interface Advanced Triggering

19 SignalTap II Design Flow
Use SignalTap II File (.STP) Use Quartus II GUI STP Separate from Design Files Use Quartus II MegaWizard Instantiate Directly into HDL

20 Using STP File Create .STP File Save .STP File & Compile with Design
Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save .STP File & Compile with Design Program Device Acquire Data

21 1) Creating a New .STP File
To Create a .STP File Method 1 Select the in Quartus II Method 2 Select New (File Menu) Other Files SignalTap II File Default File Name Will Be STP1.stp

22 Main .STP File Components
JTAG Chain Configuration Instance Manager .STP File Waveform Viewer Signal Configuration

23 Instance Manager Instance Manager Selects Current ELA to Setup/View
Displays the Current Status of each Instance Displays Size (Resource Usage) of ELA

24 Signal Configuration Manages Data Capture & Signal Configuration
Sample Clock Sample Depth Trigger Position Trigger-In & Trigger-Out

25 Assign Sample Clock Use Global Clock for Best Results
Data Written to Memory on Every Sample Clock Rising Edge Clock Signal Cannot Be Monitored as Data External Clock Pin Created Automatically if Clock Unassigned auto_stp_external_clock ELA Expects External Signal to be Connected to Clock Pin

26 Specify Sample Depth Sample Depth
Set Number of Samples Stored for each Data Signal 0 to 128K Sample Depth 0 Selected When External Analyzer Is Used Select RAM Type for Stratix & Stratix II Devices Useful when Preserving a Specific Memory Type is Necessary

27 Data Capture Circular Segmented Specify Trigger Position
Pre Center Post Continuous Segmented Specify Segment Depth

28 Circular Buffer Data is Circled through the Acquisition Buffer until the Trigger Event Occurs After the Trigger Event Occurs, Post-Trigger Data is Collected until the Buffer Fills up

29 Example: Circular Buffer

30 Segmented Buffer Segment 1 Segment 2 Segment 3 Trigger Event Acquisition Buffer is Segmented into a Smaller, User Defined Blocks Example: 4K is segmented into 4-1K segments Data is Circled through the Acquisition Buffer until the Trigger Event Occurs When the Trigger Event Occurs, Post-Trigger Data is Collected until the Segment Fills up Process Repeats until all Segments are Filled

31 Example: Segmented Buffer

32 Triggering Trigger Levels Trigger-In Trigger-Out
Indicate up to 10 Trigger Conditions Trigger-In Any I/O Pin Can Trigger the SignalTap II Analyzer Generates auto_stp_trigger_in_n Pin Trigger-Out Indicates When a Trigger Pattern Occurs Generates auto_stp_trigger_out_n Pin Delayed 4 Clock Cycles after Actual Trigger Event

33 Waveform Viewer Setup Tab Describes the Signal Settings
Data Signals vs. Trigger Signals Sets up Each Triggering Level (L1 – L10) Data Tab Displays Captured Data

34 STP File Waveform Viewer
Setup Tab Data Tab

35 Set up Waveform Viewer Add Signals to Viewer Window
Use Node Finder Main Menu, Toolbar, or Right-Click Click Only Signals that Are Found Using the SignalTap II Filter in the Node Finder Can Be Captured Important: Not All Signals Are Available Data Enable Column Check Box Controls Whether Signal Is Captured As Data Ex. Removing Reduces Sample Memory Size Trigger Enable Column Check Box Controls Whether Signal Is Disregarded as a Trigger Pattern Ex. Signal Used Only for Data Collection

36 Basic Triggering All Signals Must Be True for Level to Cause Data Capture Right-Click to Set Value

37 Debug Port Routes Data Signals to Spare I/O Pins for Capture by External Logic Analyzer Quartus II Automatically Generates auto_stp_debug_out_m_n Pin m Represents the Instance Number of the Analyzer n Represents the Order the Debug Port Pin Occurs in the Signal List

38 Mnemonic Table Allows a Set of Bit Patterns to Be Assigned User-Defined Names Right-Click in the Setup View of an STP File & Select Mnemonic Setup Select Add Table Select Add Entry Ex. State Machines or Decoders/Encoders

39 JTAG Chain Configuration
Select Programming Hardware Scan Chan Button Automatically Determines Devices Physically Connected to the Chain Detects Non-Altera Devices & Displays Them as Unknown

40 2) Save .STP File & Compile
SignalTap II Logic Analyzer Control in Compiler Settings Assignments  Settings Specify the STP File to Compile with Project

41 3) Program Device(s) Use Quartus II Programmer or STP File
Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain Use Quartus II Programmer to Program Multiple Devices Can Create a STP File for each Device in the JTAG Chain

42 4) Acquire Data SignalTap II Toolbar & STP File Controls Run Autorun
Stop Read Data (Reads in Data from Last Analysis)

43 Displaying Acquired Data
Format in Time or Sample Number Display Signal as Bar or Line Chart Export to Other Tools for Viewing or Analysis (File Menu) Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File

44 Using STP File Review Create .STP File
Assign Sample Clock Specify Sample Depth Assign Signals to STP File Specify Triggering Setup JTAG Save .STP File & Compile with Design Program Device Acquire Data

45 Using MegaWizard Create Instantiation Using MegaWizard
Number of Data Channels Sample Depth Number of Triggers Inputs Number of Trigger Levels (Advanced/Basic) Instantiate into Design Synthesize Design Create STP File Based on Instances & Edit Acquire Data

46 1) Create Instantiation
Size SignalTap II Instance Basic or Advanced Triggering?

47 2 & 3) Instantiate & Synthesize

48 4) Create STP File (File Menu) & Edit
Generates New STP File Based on Number Design Instances

49 Recompilation Recompilation Required
Addition/Removal of Instance, Data or Trigger Modifying the Sample Clock or Buffer Depth Enabling/Modifying Trigger-In/Trigger-Out Enabling the Debug Port Lock Mode Prevents Changes Requiring Recompilation

50 Incremental Routing Switches between Nodes without Full Recompilation
Maximizes Effectiveness

51 SignalTap II Incremental Routing
Switches between Nodes without Full Recompilation 1) Enable Smart Recompilation 2) Manually Set the Number of Allocated Nodes Nodes Acts as Place Holders for Real Signals that Can Be Added Later Auto Creates Enough Nodes for Current Number of Data/Triggers

52 SignalTap II Incremental Routing
Step 3: Add Post-Fitting nodes to STP file SignalTap II: Post-Fitting Nodes Always Incrementally Routed SignalTap II: Pre-Synthesis Nodes Always Cause a Full Recompilation if Added Later Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is that They Can Be Removed & Replaced with Post-fitting Nodes without a Total Recompilation Pre-Synthesis Nodes Post-fitting Nodes

53 Quartus II Netlist Optimization
New Synthesis Optimization Features Do Not Work Well with SignalTap II SignalTap II Nodes may Disappear Register Re-timing & WYSIWYG Re-Synthesis Should be Disabled if SignalTap II is Used Set the Netlist Optimizations Logic Option to Never Allow on Entities Which Have SignalTap II Nodes

54 SignalTap II & LogicLock
SignalTap II can Potentially Effect the Performance of a Design Routing and/or Placement Can Change Possible Solution: LogicLock Use LogicLock to Place Design Blocks within Specific Regions Place the SignalTap II Block in its Own LogicLock Region See Appendix for Example of Using LogicLock with SignalTap II

55 Exercise

56 SignalTap II Agenda SignalTap II Overview & Features
Using SignalTap II Interface Advanced Triggering

57 Boolean Function Composed of
Advanced Triggering Create Advanced Boolean Functions Using Pre-Synthesis Nodes Trigger Result SignalTap II Nodes Boolean Function Composed of Multiple Objects

58 Enabling Advanced Triggering
Change the Trigger Level Type from Basic to Advanced Triggering A New Advanced Trigger Tab & Window Will Appear

59 Advanced Trigger Window

60 Advanced Trigger Window
Node List Lists Available Nodes for Advanced Triggering Pre-Synthesis Nodes Only Object Library Lists Functions Necessary to Build Equations Advanced Trigger Condition Editor Graphic Tool to Build Equation

61 Object Library Object Type Settings Edge & Level Detector
Pos/Neg Edge, Levels Input Objects Bit & Bus Values Comparison Operators <, <=, =, !=, >, >= Bitwise Operators Bitwise AND, OR, XOR, Complement Logical Operators Logical NOT, AND , OR, XOR Reduction Operators Reduction AND, OR, XOR Shift Operators Left/Right Shift You Can Modify the Object Through the Properties Dialog Box Double-Click an Object Right Click Object and Select Properties

62 Advance Trigger Condition Editor
Click & Drag from Node List/Object Library into Editor

63 Advance Trigger Condition Editor
Connect Nodes & Objects Use Automatic Connection by Positioning Click & Drag Output Ports to Draw Wires

64 Advance Trigger Condition Editor
Connect to Result Block

65 Object Properties General Tab Parameter Tab Change the Object Type
Add Your Own Object Name Parameter Tab Set Bus or Bit Value Switch Between Operators of the Same Object Type Insert Pipelining Double-Click on an Object to Open Object Properties

66 Post-Fitting Nodes Results of Basic Triggering Conditions Can Be Used For Advanced Triggering

67 Example (1) Trigger on the Following Condition
If (Control =1) OR (d = F0h) AND (result = 10Fh) Pre-synthesis Nodes: Control d[7:0] Post-synthesis Node: result[11:0]

68 Edit Basic Trigger Conditions - result
Example (2) Edit Basic Trigger Conditions - result

69 Change to Advance Trigger Condition
Example (3) Change to Advance Trigger Condition

70 Add Rest of Pre-Synthesis Nodes
Example (4) Add Rest of Pre-Synthesis Nodes

71 Example (5)

72 Compiling with SignalTap II
Any Object Parameter with a White Background is Runtime Configurable Change Does Not Require a Full Compilation Any Other Changes Require a Full Compilation The User Entered Bus Value Constant is Runtime Configurable The Comparator Setting is also Run Time Configurable

73 Data Delay Delays a SignalTap II Node by a User Specified Number of Sampling Clock Cycles Object Properties Dialog Box

74 Data Delay Example Clock Instruction Register 0x01 0x02 0x03
Trigger Condition 1 If (Opcode = 0x01) followed by (Opcode = 0x02) followed by (Opcode = 0x03) Typically 4 Xilinx 10 Data delay affects latency You can view the latency in the Trigger Out Box of the Setup Tab Clock Instruction Register 0x01 0x02 0x03 Trigger Out Latency: 6 Clock Cycles

75 SignalTap II ELA Summary
Allows User to Debug Logic Design Problems during Circuit Operation at System Speed Provides Easy Setup & Visibility of Internal Nodes without External Analyzer

76 Accelerating Design Cycles Using Quartus II
SignalProbe Incremental Routing

77 SignalProbe Incremental Routing
Fast Incremental Routing of Debugging Signals (Test Points) to Spare/Reserved I/O Pins Uses Any Available Routing without Full Recompilation Debugging Cell Logic Unused I/O Used Routing Available Routing JTAG

78 SignalProbe Advantages
Simple to Use Quartus II Handles Signal Routing User Only Specifies Source Node & Destination Pin Quartus II Reports Delay Times from Node to Pin User Can Test Output of Any Hard Node Placement of Compiled Design Remains Unaffected fMAX of Signal Being Debugged Unchanged SignalProbe Uses Incremental Routing Compilation Time Typically <10% of Full Compilation Time

79 SignalProbe Supported Devices
Stratix II Stratix Stratix GX Cyclone MAX II Excalibur APEX II APEX 20K/E/C

80 Using SignalProbe Enable Smart Compilation
Assignments  Settings  Compiler Process Reserve SignalProbe Output Pins Compile Design (Optional) Assign SignalProbe Source (Debugging Nodes) Add Pipeline Registers & Clock, if Needed

81 Using SignalProbe (cont.)
Perform SignalProbe Compilation Processing  Start  Start SignalProbe Compilation Program Device Repeat Steps 4-7 to Change SignalProbe Sources

82 Assign SignalProbe Dialog Box

83 Reserve SignalProbe Pins
Select Pin Number Type Reserved Pin Name Click Add Enable SignalProbe Assign I/O Standard

84 Assign SignalProbe Sources
Use SignalProbe Filter in Node Finder to Locate Sources Assign Clock & Number of Registers for Pipelining

85 SignalProbe Sources All Sources Must Be Nodes that Exist after Fitting
Use SignalProbe Filter in Node Finder Valid Examples LE Outputs Memory Block Outputs DSP Block Outputs Invalid Examples Groups or Busses Carry or Cascade Chains

86 Editing SignalProbe Assignments
Change Source of Pins Add/Delete Source of Pins Enable/Disable SignalProbe Pins All Require SignalProbe Compilation Only Do Not Need to Perform Full Compilation

87 SignalProbe Options Route SignalProbe Signals during Full Compilation
Warning : Test Nodes May Be Synthesized Away Allow Place & Route to Be Modified (If Necessary)

88 SignalProbe Summary Allows Internal Signals to Be Routed to Unused I/O Quickly & Easily Ensures Design Placement & Routing Are Unchanged When Adding Test Points

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