1. 55:035 Computer Architecture and Organization Lecture 5

2. Outline  Adders  Comparators  Shifters  Multipliers  Dividers  Floating Point Numbers 255:035 Computer Architecture and Organization

3. Binary Representations of Numbers  To find negative numbers  Sign and magnitude: msb = ‘1’  1’s complement: complement each bit to change sign  2’s complement: 2 n – positive number b2b1b0b2b1b0 Unsigned Sign and Magnitude 1’s Complement 2’s Complement 0 1 13+3 0 1 02+2 0 0 11+1 0 0 00+0 1 0 04-0-3-4 1 0 15-2-3 1 1 06-2-2 1 1 17-3-0 355:035 Computer Architecture and Organization

4. Single-Bit Addition Half Adder Full Adder ABC out S 00 01 10 11 ABC S 000 001 010 011 100 101 110 111 4455:035 Computer Architecture and Organization

5. Single-Bit Addition Half Adder Full Adder ABC out S 0000 0101 1001 1110 ABC S 00000 00101 01001 01110 10001 10110 11010 11111 555:035 Computer Architecture and Organization

6. Carry-Ripple Adder  Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay 655:035 Computer Architecture and Organization

7. Carry Propagate Adders  N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly? 755:035 Computer Architecture and Organization

8. Propagate and Generate - Define  An n-bit adder is just a combinational circuit s i = a XOR b XOR c = a i b i ’c i ’ + a i ’b i c i ’ + a i ’b i ’c i + a i b i c i c i+1 = MAJ(a,b,c) = a i b i + a i c i + b i c i  Want to write s i in “sum of products” form c i+1 = g i + p i c i, where g i = a i b i, p i = a i + b i  if g i is true, then c i+1 is true, thus carry is generated  if p i is true, and if c i is true, c i is propagated  Note that the p i equation can also be written as p i = a i XOR b i since g i = 1 when a i = b i = 1 (i.e. generate occurs, so propagate is a “don’t care”) 855:035 Computer Architecture and Organization

9. Propagate and Generate-Lookahead  Recursively apply to eliminate carry terms c i+1 = g i + p i g i-1 + p i p i-1 g i-2 + … + p i p i-1 …p 1 g 0 + p i p i-1 …p 1 p 0 c 0  This is a carry-lookahead adder Note large fan-in of OR gate and last AND gate Too big! Build p’s and g’s in steps  c 1 = g 0 + p 0 c 0  c 2 = G 01 + P 01 c 0  Where: G 01 = g 1 + p 1 g 0, P 01 = p 1 p 0 9955:035 Computer Architecture and Organization

10. Propagate and Generate - Blocks  In the general case, for any j with i<j, j+1<k c k+1 = G ik + P ik c i G ik = G j+1,k + P j+1,k G ij P ik = P ij P j+1,k  G ik equation in words: A carry is generated out of the block consisting of bits i through k inclusive if  it is generated in the high-order part of the block (j+1, k) or  it is generated in the low-order (i,j) part of the block and then propagated through the high part 1055:035 Computer Architecture and Organization

11. PG Logic 1155:035 Computer Architecture and Organization

12. Carry-Ripple Revisited  G 03 = G 3 + P 3 G 02 1255:035 Computer Architecture and Organization

13. Carry-Skip Adder  Carry-ripple is slow through all N stages  Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal 1355:035 Computer Architecture and Organization

14. Carry-Lookahead Adder  Carry-lookahead adder computes G 0i for many bits in parallel.  Uses higher-valency cells with more than two inputs. 1455:035 Computer Architecture and Organization

15. Carry-Select Adder  Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, 1 Select proper output when X arrives  Carry-select adder precomputes n-bit sums For both possible carries into n-bit group 1555:035 Computer Architecture and Organization

16. Comparators  0’s detector:A = 00…000  1’s detector: A = 11…111  Equality comparator:A = B  Magnitude comparator:A < B 1655:035 Computer Architecture and Organization

17. 1’s & 0’s Detectors  1’s detector: N-input AND gate  0’s detector: NOTs + 1’s detector (N-input NOR) 1755:035 Computer Architecture and Organization

18. Equality Comparator  Check if each bit is equal (XNOR, aka equality gate)  1’s detect on bitwise equality 1855:035 Computer Architecture and Organization

19. Magnitude Comparator  Compute B-A and look at sign  B-A = B + ~A + 1  For unsigned numbers, carry out is sign bit 1955:035 Computer Architecture and Organization

20. Signed vs. Unsigned For signed numbers, comparison is harder  C: carry out  Z: zero (all bits of A-B are 0)  N: negative (MSB of result)  V: overflow (inputs had different signs, output sign  B) 2055:035 Computer Architecture and Organization

21. Shifters  Logical Shift: Shifts number left or right and fills with 0’s  1011 LSR 1 = ____1011 LSL1 = ____  Arithmetic Shift: Shifts number left or right. Rt shift sign extends  1011 ASR1 = ____ 1011 ASL1 = ____  Rotate: Shifts number left or right and fills with lost bits  1011 ROR1 = ____ 1011 ROL1 = ____ 2155:035 Computer Architecture and Organization

22. Shifters  Logical Shift: Shifts number left or right and fills with 0’s  1011 LSR 1 = 01011011 LSL1 = 0110  Arithmetic Shift: Shifts number left or right. Rt shift sign extends  1011 ASR1 = 11011011 ASL1 = 0110  Rotate: Shifts number left or right and fills with lost bits  1011 ROR1 = 11011011 ROL1 = 0111 2255:035 Computer Architecture and Organization

23. Funnel Shifter  A funnel shifter can do all six types of shifts  Selects N-bit field Y from 2N-bit input Shift by k bits (0  k < N) 2355:035 Computer Architecture and Organization

24. Funnel Shifter Operation  Computing N-k requires an adder 2455:035 Computer Architecture and Organization

25. Funnel Shifter Operation  Computing N-k requires an adder 2555:035 Computer Architecture and Organization

26. Funnel Shifter Operation  Computing N-k requires an adder 2655:035 Computer Architecture and Organization

27. Funnel Shifter Operation  Computing N-k requires an adder 2755:035 Computer Architecture and Organization

28. Funnel Shifter Operation  Computing N-k requires an adder 2855:035 Computer Architecture and Organization

29. Simplified Funnel Shifter  Optimize down to 2N-1 bit input 2955:035 Computer Architecture and Organization

30. Simplified Funnel Shifter  Optimize down to 2N-1 bit input 3055:035 Computer Architecture and Organization

31. Simplified Funnel Shifter  Optimize down to 2N-1 bit input 3155:035 Computer Architecture and Organization

32. Simplified Funnel Shifter  Optimize down to 2N-1 bit input 3255:035 Computer Architecture and Organization

33. Simplified Funnel Shifter  Optimize down to 2N-1 bit input 3355:035 Computer Architecture and Organization

34. Funnel Shifter Design 1  N N-input multiplexers Use 1-of-N hot select signals for shift amount 3455:035 Computer Architecture and Organization

35. Funnel Shifter Design 2  Log N stages of 2-input muxes No select decoding needed 3555:035 Computer Architecture and Organization

36. Multi-input Adders  Suppose we want to add k N-bit words Ex: 0001 + 0111 + 1101 + 0010 = _____ 3655:035 Computer Architecture and Organization

37. Multi-input Adders  Suppose we want to add k N-bit words Ex: 0001 + 0111 + 1101 + 0010 = 10111 3755:035 Computer Architecture and Organization

38. Multi-input Adders  Suppose we want to add k N-bit words Ex: 0001 + 0111 + 1101 + 0010 = 10111  Straightforward solution: k-1 N-input CPAs Large and slow 3855:035 Computer Architecture and Organization

39. Carry Save Addition A full adder sums 3 inputs and produces 2 outputs  Carry output has twice weight of sum output N full adders in parallel are called carry save adder  Produce N sums and N carry outs 3955:035 Computer Architecture and Organization

40. CSA Application  Use k-2 stages of CSAs Keep result in carry-save redundant form  Final CPA computes actual result 4055:035 Computer Architecture and Organization

41. CSA Application  Use k-2 stages of CSAs Keep result in carry-save redundant form  Final CPA computes actual result 4155:035 Computer Architecture and Organization

42. CSA Application  Use k-2 stages of CSAs Keep result in carry-save redundant form  Final CPA computes actual result 4255:035 Computer Architecture and Organization

43. Multiplication  Example: 4355:035 Computer Architecture and Organization

44. Multiplication  Example: 4455:035 Computer Architecture and Organization

45. Multiplication  Example: 4555:035 Computer Architecture and Organization

46. Multiplication  Example: 4655:035 Computer Architecture and Organization

47. Multiplication  Example: 4755:035 Computer Architecture and Organization

48. Multiplication  Example: 4855:035 Computer Architecture and Organization

49. Multiplication  Example:  M x N-bit multiplication Produce N M-bit partial products Sum these to produce M+N-bit product 4955:035 Computer Architecture and Organization

50. General Form  Multiplicand: Y = (y M-1, y M-2, …, y 1, y 0 )  Multiplier: X = (x N-1, x N-2, …, x 1, x 0 )  Product: 5055:035 Computer Architecture and Organization

51. Dot Diagram  Each dot represents a bit 5155:035 Computer Architecture and Organization

52. Array Multiplier 5255:035 Computer Architecture and Organization

53. Rectangular Array  Squash array to fit rectangular floorplan 5355:035 Computer Architecture and Organization

54. Fewer Partial Products  Array multiplier requires N partial products  If we looked at groups of r bits, we could form N/r partial products. Faster and smaller? Called radix-2 r encoding  Ex: r = 2: look at pairs of bits Form partial products of 0, Y, 2Y, 3Y First three are easy, but 3Y requires adder  5455:035 Computer Architecture and Organization

55. Booth Encoding Instead of 3Y, try –Y, then increment next partial product to add 4Y Similarly, for 2Y, try –2Y + 4Y in next partial product 5555:035 Computer Architecture and Organization

56. Booth Hardware Booth encoder generates control lines for each PP  Booth selectors choose PP bits 5655:035 Computer Architecture and Organization

57. Sign Extension Partial products can be negative  Require sign extension, which is cumbersome  High fanout on most significant bit 5755:035 Computer Architecture and Organization

58. Simplified Sign Ext.  Sign bits are either all 0’s or all 1’s Note that all 0’s is all 1’s + 1 in proper column Use this to reduce loading on MSB 5855:035 Computer Architecture and Organization

59. Even Simpler Sign Ext.  No need to add all the 1’s in hardware Precompute the answer! 5955:035 Computer Architecture and Organization

60. Division - Restoring  n times  Shift A and Q left one bit  Subtract M from A, put answer in A  If the sign of A is 1  set q 0 to 0  Add M back to A  If the sign of A is 0  set q 0 to 1 55:035 Computer Architecture and Organization60 q n1- m n1- -bit Divisor M Control sequencer Dividend Q Shift left adder a n1- a 0 q 0 m 0 a n 0 Add/Subtract Quotient setting n1+ A

61. Division – Restoring Example 61 101 11 11 01 0001

62. Division - Nonrestoring  n times  If the sign of A is 0  shift A and Q left  subtract M from A  Else  shift A and Q left  add M to A  Now if sign of A is 0  set q 0 to 1  Else  set q 0 to 0  If the sign of A is 1  add M to A 55:035 Computer Architecture and Organization62

63. Division – Nonrestoring Example 63 101 11 11 01 0001

64. Floating Point – Single Precision IEEE-754, 854 Decimal point can “move” – hence it’s “floating” Floating point is useful for scientific calculations Can represent  Very large integers and  Very small fractions  ~10 ±38 55:035 Computer Architecture and Organization64 Sign of number : 32 bits mantissa fraction 23-bit representation excess-127 exponent in 8-bit signed Value represented 001010... 0000101000 SM (a) Single precision (b) Example of a single-precision number E + 1.001010  02 87 -  = 1.M2 E127-  = 0 signifies -1 signifies

65. Floating Point – Double Precision Double Precision can represent  ~10 ±308 55:035 Computer Architecture and Organization65 52-bit mantissa fraction 11-bit excess-1023 exponent 64 bits Sign SM Value represented1.M2 E1023-  = E

66. Floating Point The IEEE Standard requires these operations, at a minimum  Add  Subtract  Multiply  Divide  Remainder  Square Root  Decimal/Binary Conversion Special Values Exceptions  Underflow, Overflow, divide by 0, inexact, invalid 55:035 Computer Architecture and Organization66 E’MValue 00+/- 0 2550+/- ∞ 0≠ 0±0.M X 2 -126 255≠ 0Not a Number NaN

67. FP Arithmetic Operations  Add/Subtract Shift mantissa of smaller exponent number right by the difference in exponents Set the exponent of the result = the larger exponent Add/Sub Mantissas, get sign Normalize  MultiplyDivide Add/Sub exponents, Subtract/Add 127 Multiply/Divide Mantissas, determine sign Normalize 55:035 Computer Architecture and Organization67

68. FP Guard Bits and Truncation  Guard bits Extra bits during intermediate steps to yield maximum accuracy in the final result  They need to be removed when generating the final result Chopping  simply remove guard bits Von Neumann rounding  if all guard bits 0, chop, else 1 Rounding  Add 1 to LSB if guard MSB = 1 55:035 Computer Architecture and Organization68

69. FP Add-Subtract Unit 55:035 Computer Architecture and Organization69