Digital Components Dr. Voicu Groza SITE Hall, Room 5017 562 5800 ext. 2159

Digital Components Dr. Voicu Groza SITE Hall, Room 5017 562 5800 ext. 2159 Groza@SITE.uOttawa.ca

CEG 2136 Computer Architecture I Outline Decoders, Multiplexers Registers + Common sense design strategies  Register with Parallel Load  Shift Registers  Bidirectional Shift Register with Parallel Load Binary Counters  Binary Counter with Parallel Load

CEG 2136 Computer Architecture I A B C D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (0) 0 0 0 1 0 0 0 0 0 0 0 (1) 0 0 1 0 1 0 0 0 0 0 0 (2) 0 1 0 0 0 1 0 0 0 0 0 (3) 0 1 1 0 0 0 1 0 0 0 0 (4) 1 0 0 0 0 0 0 1 0 0 0 (5) 1 0 1 0 0 0 0 0 1 0 0 (6) 1 1 0 0 0 0 0 0 0 1 0 (7) 1 1 1 0 0 0 0 0 0 0 1 D0D0 D2D2 D3D3 D1D1 D4D4 D5D5 D6D6 D7D7 3-to-8 Line Decoder A 2 A 1 A 0 A decoder is a combinational circuit that converts binary information from an n-bit input to a maximum of 2 n -bit output. An n-input m-output decoder is called an n-to-m line decoder, where m ≤ 2 n.

CEG 2136 Computer Architecture I A 2 A 1 A 0 E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (x) x x x 1 1 1 1 1 1 1 1 1 (0) 0 0 0 0 0 1 1 1 1 1 1 1 (1) 0 0 1 0 1 0 1 1 1 1 1 1 (2) 0 1 0 0 1 1 0 1 1 1 1 1 (3) 0 1 1 0 1 1 1 0 1 1 1 1 (4) 1 0 0 0 1 1 1 1 0 1 1 1 (5) 1 0 1 0 1 1 1 1 1 0 1 1 (6) 1 1 0 0 1 1 1 1 1 1 0 1 (7) 1 1 1 0 1 1 1 1 1 1 1 0 E A 2 A 1 A 0 D0D0 D2D2 D3D3 D1D1 D4D4 D5D5 D6D6 D7D7 3-to-8 Decoder (74 138) The Enable bit, E, enables (when E = 1, i.e. E=0) or disables (when E = 0, i.e. E=1) the functionality of the decoder. When the decoder is disabled (E = 0), all the output pins of the decoder are reset to 0:

CEG 2136 Computer Architecture I 5 Encoders An encoder is a combinational circuit that performs the opposite operation of a decoder. A 2 n -bit input n-bit output encoder generates the binary code corresponding to the input value. InputsOutputs D7D6D5 D4 D3 D2 D1 D0D7D6D5 D4 D3 D2 D1 D0 A2 A1 A0A2 A1 A0 00000001000000100000010000001000000100000010000001000000100000000000000100000010000001000000100000010000001000000100000010000000 000001010011100101110111000001010011100101110111 Truth Table for 8-to-3 Encoder When all inputs are 0’s but D 3 = 1, for instance, the output = A 2 A 1 A 0 = 011, which is the binary code for 3. A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

CEG 2136 Computer Architecture I 6 Random-access memory (RAM) Central Processing Unit (CPU) Input-output Processor (IOP) Input Devices Output Devices Memory stick DVD burner Display

CEG 2136 Computer Architecture I 4-to-1-Line Multiplexer I0I0 I1I1 I3I3 I2I2 0 1 2 3 2-to-4 decoder A 1 A 0 E Z D0D0 D2D2 D3D3 D1D1 0 1 2 3 2-to-4 decoder I0I0 I1I1 I3I3 I2I2 Z I0I0 I1I1 I3I3 I2I2 Z A1A0A1A0 I0I0 I1I1 I3I3 I2I2 Z E A 1 A 0 A multiplexer is a combinational circuit that receives binary information from one of the 2 n input data bits (I 0, I 1, …) and directs it to a single output line (Z). The selection of a particular input data bit is determined by a set of n input selection bits (A 0, A 1, …). A 1 A 0 E Z (x) x x 0 0 (0) 0 0 1 I 0 (1) 0 1 1 I 1 (2) 1 0 1 I 2 (3) 1 1 1 I 3

CEG 2136 Computer Architecture I 8 Random-access memory (RAM) Central Processing Unit (CPU) Input-output Processor (IOP) Input Devices Output Devices Memory stick DVD burner Display

CEG 2136 Computer Architecture I Registers DnDn QnQn Q n+1 000 010 101 111 Characteristic Equation: Q n+1 = D n Characteristic Table D Q CLK Q Positive-Edge -Triggered D Flip-Flop The state of the flip-flop’s output Q copies input D when the positive edge of the clock CLK occurs D CLK Q Q R Q0Q0 D Q R Q1Q1 Q1Q1 D Q R Q7Q7 Q7Q7 CL CK Q Q D0D1D7D0D1D7

CEG 2136 Computer Architecture I Common sense design strategies Focus on one bit first. In many cases the rest would have a similar pattern. Try to reason with your own words. Do the computation with “words" first. See if you can define the “rules" governing the logic circuit, and put them in your own words. The above design strategies may save you a significant amount of time and facilitate your task as a designer. However, they may not be trivial in all the cases. Register with Parallel Load CL CK D CLK Q Q R Q1 DB 1 0101 Enable = Ld/St Load/Store MUXMUX Enable Q n+1 Function 0 Q k n Store 1 DB k Load D CLK Q Q R Q1 DB 1 D CLK Q Q R Q1 DB 2 Q0 Q1 Q2 Q3 CL CK DB 1 DB 0 DB 3 Enable = Ld/St Load/Store Register => + <= DB 1 Q0Q0 Q1Q1 Q2Q2 Q3Q3 DB 2 DB 3 DB 0 Next State Logic CC S n+1 = δ(S n,X n ) State Register Flip Flops CL Enable = Ld/St Load/Store

CEG 2136 Computer Architecture I Register with Parallel Load => D k = Enable DB k + Enable Q k ; k={0,1,2,3} The transition function (δ) of the Parallel Register to be designed: Q k (n+1) = Ld DB k + St Q k (n); k={0,1,2,3} =Enable DB k + Enable Q k ; If the Parallel Register is implemented with D-FF's, its excitation equation gives: D(n) = Q k (n+1) Enable Q n+1 Function 0 (St) Q k n Store 1 (Ld) DB k Load Enable = Ld / St When the load input Ld / St = 1, at the positive clock pulse transition time, the data in the four input bits DB 0 is transferred into the register; otherwise when load input Ld / St = 0, the register output bits maintain their values.

CEG 2136 Computer Architecture I Shift Registers A shift register is a register that is capable of shifting its binary information in one or both directions. The logical configuration of a shift register consists of a chain of cascaded flip-flops. The output of each flip-flop is connected to the input of the next flip-flop. serial input serial output clock The serial input denotes the external input fed into the shift register. The serial output denotes the data that is not fed into any of the register’s flip-flops. 14 D Q C D Q C D Q C D Q C

CEG 2136 Computer Architecture I 15 tt t t t Clock Q3Q2 Q1Q0 = Serial Output Right Shift Register Serial Input = 0 Initial State: t 0 : Q 3 Q 2 Q 1 Q 0 =1000 t 1 : Q 3 Q 2 Q 1 Q 0 =0100 t 2 : Q 3 Q 2 Q 1 Q 0 =0010 t 3 : Q 3 Q 2 Q 1 Q 0 =0001 D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C Serial Input = 0 t 0 t 1 t 2 t 3

CEG 2136 Computer Architecture I Right Shift Register tt t t t Clock Q3Q2 Q1Q0 = Serial Output D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C Serial Input = 1 D Q C D Q C D Q C D Q C Serial Input = 1 Initial State: 0000 t 1 : Q 3 Q 2 Q 1 Q 0 =1000 t 2 : Q 3 Q 2 Q 1 Q 0 =1100 t 3 : Q 3 Q 2 Q 1 Q 0 =1110 t 4 : Q 3 Q 2 Q 1 Q 0 =1111 0t1 t2t3 t40t1 t2t3 t4

CEG 2136 Computer Architecture I 17 Serial transfer from register X to register Y 1 0 1 0 0 0

CEG 2136 Computer Architecture I TDI Ck DQDQ f(0,0,0) 0 Ck DQDQ f(0,0,1) 1 Ck DQDQ f(0,1,0) 2 Ck DQDQ f(0,1,1) M 3 Ck DQDQ f(1,0,0) U f(A,B,C) 4 Ck DQDQ f(1,0,1) X 5 Ck DQDQ f(1,1,0) 6 Ck DQDQ f(1,1,1) 7 ABCf(A,B,C) Memory ABC 000f(0,0,0) = M 0 | | | 001f(0,0,1) = M 1 1 010f(0,1,0) = M 2 2 M 011f(0,1,1) = M 3 3 U f(A,B,C) 100f(1,0,0) = M 4 4 X 101f(1,0,1) = M 5 5 110f(1,1,0) = M 6 6 111f(1,1,1) = M 7 7 FPGA Programmable Logic Element (LE) Truth Table Programmable Logic Element „Programmable Inverter” TDO Clk·Prog

CEG 2136 Computer Architecture I FPGA 19 I/O Memory Multiplier LE Memory Multiplier LE Memory Multiplier LE Memory Multiplier LE I/O

CEG 2136 Computer Architecture I Multi-function Registers The most general register (Bidirectional Shift Register and Parallel Load) has the following capabilities: 1. A clock pulse input to synchronize all operations. 2. A shift right operation and a serial input line associated to it. 3. A shift left operation and a serial input line associated to it. 4. A parallel load operation and n input lines associated to it. 5. n parallel output lines 6. A “no change” control state to leave the n parallel output lines unchanged for the next clock pulse. 21 Mode Control S1S1 S0S0 Register operation 00No change 01Shift right (msb->lsb) 10Shift left (lsb->msb) 11Parallel load

CEG 2136 Computer Architecture I Top-down design S 1 S 0 Function (f 0 ) 0 0 No Change=Store (f 1 ) 0 1 Shift Right =down: msb->lsb & D 3 =Serial In (f 2 ) 1 0 Shift Left = up: msb->lsb & D o = Serial In (f 3 ) 1 1 Parallel Load DB Bidirectional Shift Register and Parallel Load with D Flip Flops I1I1 A 3 (msb) A2A2 A1A1 A 0 (lsb) S1S1 S0S0 I2I2 I3I3 I0I0 Serial In Register

CEG 2136 Computer Architecture I Top-down design S 1 S 0 A k n+1 Function (f 0 ) 0 0 A k n No Change=Store (k={0,1,2,3}) (f 1 ) 0 1 A n k+1 Shift Right (k={0,1,2}: msb->lsb & D 3 =Serial In) (f 2 ) 1 0 A n k-1 Shift Left (k={1,2,3}: lsb => msb & D 0 =Serial In) (f 3 ) 1 1 I k Parallel Load (k={0,1,2,3}) Bidirectional Shift Register and Parallel Load with D Flip Flops S 1 S 0 D k = A k n+1 (f 0 ) 0 0 D k = A k ; k={0,1,2,3} (f 1 ) 0 1 D k = A k+1 ; k={0,1,2} D 3 =Serial In) (f 2 ) 1 0 D k = A k-1 ; k={1,2,3} D 0 =Serial In) (f 3 ) 1 1 D k = I k ; k={0,1,2,3} I1I1 A 3 (msb) A2A2 A1A1 A 0 (lsb) S1S1 S0S0 I2I2 I3I3 I0I0 Serial In Register I1I1 Q3Q3 Q2Q2 Q1Q1 Q0Q0 S1S1 S0S0 I2I2 I3I3 I0I0 Next State Logic CC S n+1 = δ(S n,X n ) State Register Flip Flops Serial In

CEG 2136 Computer Architecture I 24 Four ‐ bit universal shift register

CEG 2136 Computer Architecture I = Register that goes through a prescribed series of states There are two main types of counters: 1.Asynchronous counters: also known as Ripple counters - Flip flop’s output’s serve as clock for triggering connected flip flops 2.Synchronous counters – All flip flops are triggered by a clock signal at the same time Counters 26 Q0 Q1 Q2 clk

CEG 2136 Computer Architecture I Modulo 16 Synchronous Counter using D Flip-Flops Q =  Qi. 2 i i = 0 3 0 1 2 3 45 10 98 11 12 13 6 7 15 14 Q3Q1 Q0 Q2 CK 4-Bit BINARY COUNTER CL 1 0 CK Q 0 1 2 3 4 5 6 7 89 10 11 12 13 14 15 01 2 3 4 5 6 CL 1 0 The number of unique states that a counter may have before the sequence repeats itself is the modulus of the counter The number of unique states that a counter may go through before the count sequence repeats itself is the modulus (or MOD) of the counter.

CEG 2136 Computer Architecture I DECIMAL Present STATE OF The next state = STATE THE COUNTER FLIP FLOP INPUTS Q Q3 Q2 Q1 Q0 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 2 0 0 1 0 0 0 1 1 3 0 0 1 1 0 1 0 0 4 0 1 0 0 0 1 0 1 5 0 1 0 1 0 1 1 0 6 0 1 1 0 0 1 1 1 7 0 1 1 1 1 0 0 0 8 1 0 0 0 1 0 0 1 9 1 0 0 1 1 0 1 0 10 1 0 1 0 1 0 1 1 11 1 0 1 1 1 1 0 0 12 1 1 0 0 1 1 0 1 13 1 1 0 1 1 1 1 0 14 1 1 1 0 1 1 1 1 15 1 1 1 1 0 0 0 0 Using D flip-flops has the distinct advantage of a straightforward definition of the flip-flop inputs: the current state of these inputs is the next state of the counter. The logic equations for all four flip-flop inputs D3, D2, D1, and D0 are derived from this truth table as functions of the current states of the counter’s flip-flops: Q3, Q2, Q1, and Q0. Karnaugh maps can be used to simplify these equations. Q1 Q0 Q3 Q2 00 01 11 10 00 0 1 1 0 1 0 0 1 0 1 1 0 01 11 10 D2 Q1 Q0 Q3 Q2 00 01 11 10 00 0 0 1 1 0 1 0 0 1 1 01 11 10 D3 Q1 Q0 Q3 Q2 00 01 11 10 00 1 1 0 0 1 1 01 11 10 D1 Q1 Q0 Q3 Q2 00 01 11 10 00 1 1 0 0 1 1 01 11 10 D0 Modulo 16 Synchronous Counter Q1 Q0 Q3 Q2 00 01 11 10 00 0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 01 11 10

CEG 2136 Computer Architecture I Q1 Q0 Q3 Q2 00 01 11 10 00 0 1 1 0 1 0 0 1 01 11 10 D2 0 1 1 0 Q1 Q0 Q3 Q2 00 01 11 10 00 01 11 10 D1 1 1 D3 = Q3. Q2 + Q3. Q1 + Q3. Q0 + Q3. Q2. Q1. Q0 D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0 D1 = Q1. Q0 + Q1. Q0 D0 = Q0 Q1 Q0 Q3 Q2 00 01 11 10 00 1 1 0 0 1 1 01 11 10 D0 Q1 Q0 Q3 Q2 00 01 11 10 00 01 11 10 D3 0 0 1 1 0 1 0 0 1 1 Modulo 16 Synchronous Counter Excitation Equations D n = Q n+1

CEG 2136 Computer Architecture I D3 = Q3. Q2 + Q3. Q1 + Q3. Q0 + Q3. Q2. Q1. Q0 D2 = Q2. Q0 + Q2. Q1 + Q2. Q1. Q0 D1 = Q1. Q0 + Q1. Q0 D0 = Q0 D CLK Q Q R Q0 D CLK Q Q R Q1 D CLK Q Q R Q2 D CLK Q Q R Q3 CL CK Modulo 16 Synchronous Counter Implementation D n = Q n+1

CEG 2136 Computer Architecture I Binary Counter Modulo 16 Synchronous Counter using JK Flip-Flops A =  A i. 2 i i = 0 3 0 1 2 3 45 10 98 11 12 13 6 7 15 14 A3A3 A1A1 A0A0 A2A2 CK 4-Bit BINARY COUNTER CL 1 0 CK A 0 1 2 3 4 5 6 7 89 10 11 12 13 14 15 01 2 3 4 5 6 CL 1 0

CEG 2136 Computer Architecture I Present state S n Next state S n +1 A3A3 A2A2 A1A1 A0A0 A3+A3+ A2+A2+ A1+A1+ A0+A0+ 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10011010 10101011 10111100 11001101 11011110 11101111 11110000 A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 We can notice from the State Table that: A 0 toggles its value at each clock pulse => J 0 = 1 ; K 0 = 1. A 1 toggles its value at time T only if at time (T - 1) A 0 is 1. A 2 toggles its value at time T only if at time (T - 1) A 1 = 1 and A 0 = 1 Present StateNext StateFlip-Flop Inputs A 2 (T − 1) A 1 (T − 1) A 0 (T − 1) A 1 (T ) J1K1J1K1 x x0 x x1 A 1 (t − 1) (A 1 (t − 1))’01 J 1 = K 1 = A 0 (T - 1) Present State Next StateFlip-Flop Inputs A 2 (T − 1)A 1 (T − 1)A 0 (T − 1)A 2 (T )J 2 K 2 x00A 2 (t − 1)0 x01A 2 (t − 1)0 x10A 2 (t − 1)0 x11(A 2 (t − 1))'1 J 2 = K 2 = A 1 (T - 1) A 0 (T - 1) “Common sense” design approach

CEG 2136 Computer Architecture I Present state S n Next state S n +1 A 3 inputA 2 inputA 1 inputA 0 input A3A3 A2A2 A1A1 A0A0 A3+A3+ A2+A2+ A1+A1+ A0+A0+ J3J3 K3K3 J2J2 K2K2 J1J1 K1K1 J0J0 K0K0 000000010x0x0x1x 000100100x0x1xx1 001000110x0xx01x 001101000x1xx1x1 010001010xx00x1x 010101100xx01xx1 011001110xx0x01x 011110001xx1x1x1 10001001x00x0x1x 10011010x00x1xx1 10101011x00xx01x 10111100x01xx1x1 11001101x0x00x1x 11011110x0x01xx1 11101111x0x0x01x 11110000x1x1x1x1 A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 33 Use the “Common sense” design approach -> see next slide

CEG 2136 Computer Architecture I Top-down design D0D0 CLK Q Q R Q 0 (lsb) Q1Q1 Q2Q2 CL CK MUXMUX 01230123 S1S0S1S0 D1D1 CLK Q Q R MUXMUX 01230123 D2D2 Q Q R MUXMUX f21f21 01230123 f20f20 f23f23 f22f22 f01f01 f00f00 f03f03 f02f02 f11f11 f10f10 f13f13 f12f12 Q 3 (msb) D3D3 CLK Q Q R MUXMUX f31f31 01230123 f30f30 f33f33 f32f32 S 1 S 0 Q k n+1 Function (f 0 ) 0 0 Q k n Store (f 1 ) 0 1 N k Count up (f 2 ) 1 0 DB k Load (f 3 ) 1 1 0 Clear Multifunction Register with D-Flip Flops k = {0,1,2,3} DB 1 Q 3 (msb) Q2Q2 Q1Q1 Q 0 (lsb) S1S1 S0S0 DB 2 DB 3 DB 0 Multifunction Register DB 1 Q3Q3 Q2Q2 Q1Q1 Q0Q0 S1S1 S0S0 DB 2 DB 3 DB 0 Next State Logic CC S n+1 = δ(S n,X n ) State Register Flip Flops Multifunction Register implemented as a Sequential Circuit

CEG 2136 Computer Architecture I DB 2 D CLK Q Q R Q0 D CLK Q Q R Q1 D CLK Q Q R Q2 D CLK Q Q R Q3 CL CK DB 1 DB 0 DB 3 MUXMUX 01230123 S 1 S 0 2 MUXMUX 01230123 MUXMUX 01230123 MUXMUX 01230123 0 0 0 0 Multifunction Register S 1 S 0 D k = Q k n+1 Function (f 0 ) 0 0 Q k n Store (f 1 ) 0 1 N k Count up (f 2 ) 1 0 DB k Load (f 3 ) 1 1 0 Clear f21f21 f01f01 f11f11 f31f31 Use the “Common sense” design approach, (where obvious) or: D- FF’s excitation equation: D n = Q n+1 (1) Store (f 0 ): Q n+1 = Q n (2) to be implemented with D-FF From (1), (2) => D n = Q n+1 = Q n i.e., D k = Q k, k ={0,1,2,3} Clear (f 3 ): Q n+1 = 0 (3) with D-FF From (1), (3) => D n = 0 i.e., D k = 0, k ={0,1,2,3} Load (f 2 ): Q n+1 = DB n (4) with D-FF From (1), (4) => D n = DB n, i.e., D k = DB k, k ={0,1,2,3}

CEG 2136 Computer Architecture I Multifunction Register - Count up (f 2 ) D CLK Q Q R Q0Q0 D Q Q R Q1Q1 Q1Q1 D Q Q R Q2Q2 Q2Q2 D Q Q R Q3Q3 Q3Q3 CK Q3Q3 Q2Q2 Q1Q1 Q0Q0 Q3+Q3+ Q2+Q2+ Q1+Q1+ Q0+Q0+ D3D3 D2D2 D1D1 D0D0 000000010001 000100100010 001000110011 001101000100 010001010101 010101100110 011001110111 011110001000 100010011001 100110101010 101010111011 101111001100 110011011101 110111101110 111011111111 111100000000 CLR Q0’Q0’

CEG 2136 Computer Architecture I DB 2 D CLK Q Q R Q0 D CLK Q Q R Q1 D CLK Q Q R Q2 D CLK Q Q R Q3 CL CK DB 1 DB 0 DB 3 MUXMUX 01230123 A 1 A 0 2 MUXMUX 01230123 MUXMUX 01230123 MUXMUX 01230123 0 0 0 0 Multifunction Register Implementation A 1 A 0 D k = Q k n+1 Function (f 0 ) 0 0 Q k n Store (f 1 ) 0 1 N k Count up (f 2 ) 1 0 DB k Load (f 3 ) 1 1 0 Clear

CEG 2136 Computer Architecture I 4-bit Binary Counter with Parallel Load & Synchronous Clear with JK FF A 1 A 0 Q k n+1 Function (f 0 ) 0 0 Q k n Store = No change (f 1 ) 0 1 N k Increment (Count up) (f 2 ) 1 0 DB k Load (f 3 ) 1 1 0 Clear k = {0,1,2,3} S 1 S 0 E D0D0 D2D2 D3D3 D1D1 0 1 2 3 2-to-4 decoder DI 0 DI 1 DI 3 DI 2 Z MUX

CEG 2136 Computer Architecture I I State table of Sequential Circuit to be Designed Design D-Latch using JK FF JK Excitation Table DQnQn Q n+1 JK 0000x 010 x1 101 1x 111x0 QtQt Q t+Δt JtJt KtKt 000x 011x 10x1 11x0 QJ K D δ D QJ K D J 0 0 0 1 D Q n 0 1 0 1 2 x 3 1 x 0 1 1 K D D Q n 0 1 0 x 2 0 3 1 J = D K = D II 4 4 5 Step 3 Step 4: SR input equations Step 5 Excitation table for Sequential Circuit to be Designed 4 Step 1 : Initial State table D Q n Q n+1 0 1 1 0 1 1 0 1 Given: D-Latch Characteristic Table 1 START HERE 0 0 Clock

CEG 2136 Computer Architecture I BUS INPR LD TR INR TR CLR TR OUTR LD OUTR 16 TR Memory D in Addr D out Write Read AR LD AR INR AR CLR AR PC LD PC INR PC CLR PC 12 16 IR LD IR 16 71256347125634 Data path S 2 -S 0 Sel BASICCOMPUTERBASICCOMPUTER DR LD DR INR DR CLR DR AC LD AC INR AC CLR AC ALU AND,ADD DR,INPR, COM,SHR Control Unit CPUCPU Most registers of the Basic Computer are implemented on the basis of the logic diagram of the two multifunctional registers designed above. Memory CPU (Registers, ALU & CU) Data Bus Address Bus Control Bus

CEG 2136 Computer Architecture I 42 2-to-4 decoder S 3 S 2 S 1 S 0 State Encoding mod 4 counter Full Encoding: BINARY COUNTER 1-hot Encoding: RING COUNTER 1 S 3 S 2 S 1 S 0 D Q C D Q C D Q C D Q C T Q C T Q C Clock

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