1. Memory - 2 10/27/081ECE 561 - Lecture 13 Memory 2

2. Memory The internal structure of the ICs ROM Types and RAM 10/27/082ECE 561 - Lecture 13 Memory 2

3. Memory Types How a ROM works 10/27/083ECE 561 - Lecture 13 Memory 2

4. A 128 x 1 ROM The basic structure 10/27/084ECE 561 - Lecture 13 Memory 2

5. Larger Array Sizes Arranged in blocks 10/27/08ECE 561 - Lecture 13 Memory 25

6. Commercial ROM Types Table 9-5 – Type Tech ReadCyc WrCyc Comments – MASK ROM NMOS 10-100ns 4 weeks Write once, low pwr – CMOS – MASK ROM Bipolar <100ns 4 weeks Write once, h pwr – low density – PROM Bipolar <100ns 10-50us/byte Write once, h pwr – EPROM NMOS 25-200ns 10-50us/byte Reusable, low pwr – CMOS – EEPROM NMOS 50-200ns 10-50us/byte 10,000 to 100,000 – writes per location 10/27/08ECE 561 - Lecture 13 Memory 26

7. EPROM Erasable Programable Read Only Memory 10/27/08ECE 561 - Lecture 13 Memory 27

8. EPROM Uses a floating gate for the FET at each bit location User uses a programming voltage that causes a temporary breakdown in the dielectric between the gate and the floating gate to charge it. When programming voltage is removed the charge stays How long? EPROM manufacturers “guarantee” properly programmed bit has 70% of charge after 10 years. Use UV light to erase 10/27/08ECE 561 - Lecture 13 Memory 28

9. EEPROM Electrically Erasable PROM Like the EPROM only electrically erasable in circuit. Many times referred to a “flash” programmable memory Very slow on writes so not a substitute for RAM 10/27/08ECE 561 - Lecture 13 Memory 29

10. General Block Diagram 10/27/08ECE 561 - Lecture 13 Memory 210 xROM

11. General Timing General timing parameters 10/27/08ECE 561 - Lecture 13 Memory 211

12. The timing parameters Access time from address – t AA Access time from chip select - t ACS Output-enable time - t OE Output-disable time - t OZ Output-hold time - t OH 10/27/08ECE 561 - Lecture 13 Memory 212

13. R/W Memory Memory to store and retrieve data when more than F/Fs A few types Static RAM – SRAM – As long as power is maintained data is held 10/27/08ECE 561 - Lecture 13 Memory 213

14. SRAM The data storage 10/27/08ECE 561 - Lecture 13 Memory 214

15. A static RAM chip Internal – an arrangement of storage sturctures 10/27/08ECE 561 - Lecture 13 Memory 215

16. SRAM Timing Timing for write similar (see Fig 9-23) 10/27/08ECE 561 - Lecture 13 Memory 216

17. DRAM Next step in memory is Synchronous SRAM which has a clocked interface for control, address and data. Then comes DRAM – dynamic ram In DRAM data is stored in a semiconductor capicator. 10/27/08ECE 561 - Lecture 13 Memory 217

18. DRAM Read A read sees the bit line precharged to high. The word line is then activated If cell stores a 0 then there is a small drop on the voltage on the bit line This is monitored by a sense amp which provides the value stored Value must be written back after the read. 10/27/08ECE 561 - Lecture 13 Memory 218

19. DRAM Refresh Charge stored leaks off over time Must restore the values stored – A 4096 row DRAM – refresh every 64ms – Thus each row every 15.6 usec Larger DRAMs are banks of smaller 10/27/08ECE 561 - Lecture 13 Memory 219

20. DDR SDRAM Double data rate SDRAM Double the data transfer rate of an SDRAM by transferring on both edges of the clock Access and setup times are the same as SRAM Increased data thruput as data is transferred in blocks. 10/27/08ECE 561 - Lecture 13 Memory 220