1. Design of a 10 Bit TSMC 0.25μm CMOS Digital to Analog Converter Proceedings of the Sixth International Symposium on Quality Electronic Design IEEE, 2005 指導老師 : 易序忠 班級 ：積體碩一 姓名 ：黃順和 學號 ： 95662009

2. Outline 1. Introduction 2. Circuit Design 3. Project Implementation and Performance Results 4. Conclusion 5. References

3. Introduction High resolution digital analog converters (DACs) are highly demanded in today’s wireless communication applications. Several digital to analog architectures for DAC designs were discussed.Those architectures included resistor string, R-2R ladder networks, charge scaling, current steering, and segmented current steering. A low pass filter placed after the output terminal of the converter is necessary to make the voltage level smooth.

4. Circuit Design In this project, the proposed 10-bit digital to analog converter was designed, analyzed, implemented, simulated, and layout in a 0.25μm CMOS technology. The 10-bit converter consists of three digital to analog converters. The first one is an 8-bit thermometer coded DAC.The second and the third DAC are two 1-bit binary weighted DACs.

6. Design of a Current Source Block The analog part of a current source block consists of a cascoded current source and a differential switch. PMOS devices are employed in the current source because they reduce cross-talk. A current source also includes buffers to drive a differential switch.

7. Design of a Low Pass Filter

8. Designs of Inverters and Buffers

9. Design of the Bandgap Reference Voltage Circuit The bandgap reference voltage is used to provide the temperature invariant voltage for an integrated circuit. As temperature increasing, V BE is dropped by 2mV per degree C; however, thermal voltage is increased by 0.085mV per degree C. V ref = V be + KV PTAT V be is the forward biased voltage of a diode.

10. Project Implementation and Performance Results The period of the clock is 20ns which is equivalent to 50MHz. The 1 LSB cascoded current cell conducts 20μA as expected. In addition, each input has 100ps for rise time and 100ps for fall time.

11. In addition, the MatLab program is used to draw the plot for gain error calculation, integral nonlinearity (INL), and differential nonlinearity (DNL) characteristics for the 10-bit DAC. From the worst case for gain error plot, the worst case of the gain error for the 10-bit DAC at 0.002V is about 1.3LSB.

12. The test bench includes the biasing current circuit, the 10 bit DAC, the low pass filter, and the bandgap circuit. An output load of the 10 bit DAC is 50f. The supply voltage is 2.5V. The power consumption of the DAC is about 52mW.

14. Conclusion Design of a 10-bit segmented current steering TSMC 0.25μm CMOS digital to analog converter (DAC) was done in this project. The power consumption of this 10-bit converter was reduced by half compared to the 10-bit converter which was done by Park, Cho, and Yoon[1]. The function of the low pass filter is to filter out noises at high frequencies and it also makes the output of the DAC smooth.

15. References [1]. S.Y. Park, H. H. Cho, and K. H. Yoon, “A 3.3V-110MHz 10-Bit CMOS Current Mode DAC,” CATS, 2001. [2] T. Miki, Y. Nakamura, M. Nakamura, Y. Akasaka, and Y. Horiba, “An 80MHz 8 bit CMOS D/A Converter,” IEEE J. Solid-State Circuits, pp.983-998, Dec.1986.