1. Internal Input/Output Devices (I/O Subsystems)
ECE Lecture 2
Internal Input/Output
Devices (I/O Subsystems)

2. Organization of MC68HC11 in the Single-Chip Mode
RAM
CPU
ROM
EEPROM
A/D
SPI
TIMER
SCI
8 (4) 8 4 2
PORT A
PORT B
PORT C
PORT D
PORT E 3 3 2 8 8 6
8 (4)

3. Abbreviations CPU - Central Processing Unit
:= ALU (Arithmetic Logic Unit) + Control
RAM - Random Access Memory := Read/Write Memory
ROM - Read Only Memory (non-volatile)
EPROM - Erasable Programmable ROM
EEPROM - Electrically Erasable ROM
SCI - Serial Communication Interface
(asynchronous serial communication interface)
SPI - Serial Peripheral Interface
(synchronous serial communication interface)
A/D - analog-to-digital converter

4. Input/Output Ports Input Pins Output Pins Bidirectional Pins Shared
Functions
Port
Port A
Port B
Port C
Port D
Port E 3 – 8 3 8 – 2 – 8 6
Timer
High Order Address
Low Order Address
and Data Bus
SCI and SPI
A/D Converter

5. Capabilities of the A/D converter
VRH  6 V
> 2.5 V
VRL  0 V
successive approximation
minimum 4 conversions
single-channel or four-channel conversions
one-time or continuous conversions

6. Capabilities of the 68HC11 timer (1)
1. Generating delays - imposing a specific delay between
two points in the program
label 1
instr1
instr2
delay
label2
instrN
2. Pulse accumulation - counting the number of pulses

7. Capabilities of the 68HC11 timer (2)
3. Input capture - measuring the time between signal
edges
start
stop
start
stop
4. Output compare - generating signals with the given
timing characteristics
single pulse
periodical signal
pulse width
period

8. I/O Device Architecture
Control registers
instructions
address1/name1
…..
Status registers
status of the device
…..
Data registers
inputs (operands)
…..
addressN/nameN
outputs (results)

9. Input/Output Register Types
1. Control registers - hold instructions that regulate the operation of
internal I/O devices
2. Status registers - indicate the current status of internal I/O devices
3. Data registers - hold the input data sent to the I/O device and output
data generated by this device
4. Data direction registers - control the direction (in or out) of the data
flow to/from bidirectional data registers

10. Memory mapped I/O
Separate I/O
(e.g., Intel)
(e.g., Motorola)
I/O
max
I/O
MAX
MAX
Control lines:
read/write
Control lines:
read/write
memory/io

11. Memory map of MC68HC11E9 $0000-$01FF $0000 512 bytes RAM $1000
64 bytes I/O registers
$B600
$B600-$B7FF
512 bytes EEPROM
$D000
$D000-$FFFF
12 kbytes ROM
$FFFF
Single-chip mode

12. Memory map of MC68HC11E1 $0000-$01FF $0000 512 bytes RAM $1000
64 bytes I/O registers
$B600
$B600-$B7FF
512 bytes EEPROM
$FFFF
Single-chip mode

13. in the Expanded Bus Mode
Organization of MC68HC11
in the Expanded Bus Mode
RAM
CPU
ROM
EEPROM
A/D
SPI
TIMER
SCI
8 (4) 8 4 2
PORT A
PORT D
PORT E 6
8 (4) 3 3 2
EXTERNAL RAM
EXTERNAL EPROM
EXTERNAL ROM
EXTERNAL I/O

14. Memory map of MC68HC11E1 $0000 $0000 $0000-$01FF 512 bytes RAM $1000
EXT
$1000
$1000
$1000-$103F
64 bytes I/O registers
EXT
$B600
$B600
$B600-$B7FF
512 bytes EEPROM
EXT
$FFFF
$FFFF
Single-chip mode
Expanded bus mode

15. Evaluation Board Configuration
68HC11E9 A
68HC24 - Port Replacement Unit
RAM
512B
EEPROM B B
512B C C E D
ROM
(e.g., 2764)
RAM
(e.g. 5164)
Program
& data
Buffalo
monitor
12 kB
$D000-$FFFF
50 kB
$2000-$B5FF

16. Memory map of MC68HC11E9 with an external RAM
$0000-$01FF
512 bytes RAM
$0000
$1000
$1000-$103F
64 bytes I/O registers
$A5ff
$0000-$B5ff
32 kbytes RAM
$B600
$B600-$B7FF
512 bytes EEPROM
$D000
$D000-$FFFF
12 kbytes ROM
$FFFF
Expanded bus mode