1. Understanding Data Acquisition System for N- XYTER

2. Set-up Requirements Measurement of time, energy and position Data acquisition speed ~ 1Gbps Input Clock ~ 250MHz Input channels ~ 1024 or higher Data - 8-bit parallel after flash ADC ADC – Flash type 8-bit (MAX-106 600MSPS) Time stamp, channel-ID and status signals 32 bit(8-bit parallel x 4 packet)

3. N-XYTER Block Schematic

5. Data packet for time-stamp channel- id and status signals Differential analog output in N-XYTER

6. Some parameters form CBM Each channel detects autonomously all hits An absolute time stamp, precise to a fraction of the sampling period, is associated with each hit All hits are shipped to the next layer (usually concentrators) Association of hits with events done later using time correlation Typical Parameters: –with few 1% occupancy and 10 7 interaction rate: some 100 kHz channel hit rate few MByte/sec per channel whole CBM detector: 1 Tbyte/

7. 1Gbps FOL Basic Idea for Readout for 4-chip FEE board FEE-board Readout controller (ROC) Serial fiber optic peripheral

8. Basic n-XYTER Readout Chain Detector FEBROC XYTER ADC XYTER Tag data ADC data clock FPGA control SFP MGT ABB FPGA MGT Front-End Board Read-Out Controller Active Buffer Board Bond or cable connection up to 8 N-XYTER 1024 ch. LVDS signal cable 2.5 Gbps optical link 1-4 lane PCIe interface

9. Scalable n-XYTER Readout Chain Detector FEBROC XYTER ADC XYTER Tag data ADC data clock FPGA control SFP MGT DCB FPGA SFP MGT Front-End Board Read-Out Controller Data Combiner Board to other ROC's to ABB SFP MGT

10. PC Some Configurations DetectorFEBROC ABB PC DCB ABB DetectorFEBROC DetectorFEBROC DetectorFEBROC DetectorFEBROC Minimal Configuration Expandable Configuration Data Combiner Board

11. OLDER READOUT EXPERIENCE MANAS MARC ADC FEE BOARD TRANSLATOR BOARD DAQ LVTTL DATA and CONTROL lines LVDS LINK

12. Proposed idea to have the test set-up Exixting CROCUS DAQ can be used as ABB card just to make the ROC card with FEE board 1Gbps link ROC FEE External board with FPGA and Buffer SIU used in CROCUS DAQ

13. Proposed N-XYTER Readout scheme NXYTERNXYTER NXYTERNXYTER NXYTERNXYTER NXYTERNXYTER ADC ASIC based ROC LVDS CONTROL and DATA lines DCB with 10 Gbps SFP link FEE BOARD To other FEE boards OFC link DAQ

14. Readout controller (ROC) board Raw data and memory management Data acquisition and processing (data tagging). Data transfer at 1Gbps by Multi gigabyte Tran-receiver (MGT) and then send via serial fiber optic link of 1Gbps I2C driver for N-XYTER configuration and slow control.

15. Control bus to N-XYTER To FOL 1Gbps link

16. N-XYTER Chip configuration All internal bias, thresholds and DAC references are programmable through I2C slow control @ 100Kbps by total 46 resisters. ROC board is to be built to program and to control above mentioned control resisters and FPGA program can be changed by JTAG port. Next slide shows proposed scheme for N- XYTER configuration and control through I2C bus.

19. N-XYTER SDA SLC FPGA I2C_ID0I2C_ID6I2C_ID0I2C_ID6I2C_ID0I2C_ID6I2C_ID0I2C_ID6 I2C Programming Scheme

20. Algorithm Configuration data to be entered form computer to FPGA via RS-232 interface and stored in IIC EPROM. On start or restart of the system configuration data to be transferred to the N-XYTER through IIC bus. Status resister can be read back from N- XYTER through RS-232 port.

21. For configuration of the XYTER to set the threshold values and control words, a LINUX based platform is used in the PC. The software in the PC extend the facility to configure all the control Words and the same can be down loaded to the EEPROM on the ROC board through RS232 link. The EEPROM is connected through a IIC bus to FPGA and configure the XYTER with SOFTWARE CONTROL from the PC The ROCKET IO/ GTP provide data at 1GBPS in the serial format The standard Desk Top PC has a limitation to acquire data at 1GBPS so a SERVER is required to handle the High-speed data @1gbps from the ROC board through light link JTAG PROGRAMMING –The FPGA selected are nonvolatile and reprogrammable. However for programming the JTAG port is available at the board. –We require XILINX ISE software and JTAG Cable for development and downloading the software. Computer Control

22. UART-BLOCK RS-232 BUS- Controller Block Center Control- Block GTP- Controller SIU SERVER MEMORY I/O and Contol Bus to N-Xyter

23. V-4 MGT based optical link V-4 MGT based PCI-Express interface (4 lanes) Active Buffer Board This board is under construction and is expected soon.

24. Thank You