1. P. Baron CEA IRFU/SEDI/LDEFACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 1 Functionality of AFTER+ chip applications & requirements At this time, AFTER+ must fit the specifications of: ACTAR/GANIL TPC/GLAD/R3B/FAIR TPC&ACTIVE TARGET/MSU TPC/CENBG SAMURAI TPC/RIKEN …

2. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 2 AFTER+: Architecture Main features for AFTER+: 72 Analog Channels; Slow Control & test [“spy” mode].72 Analog Channels; Slow Control & test [“spy” mode]. Main features for the channel Input Current Polarity: positive or negative.Input Current Polarity: positive or negative. CSA + PZC + Filter (semi-Gaussian order 2).CSA + PZC + Filter (semi-Gaussian order 2). [Possibility to bypass the CSA]. SCA: 511 analog memory cells.SCA: 511 analog memory cells. Auto Triggering: discriminator + threshold (DAC) + inhibition.Auto Triggering: discriminator + threshold (DAC) + inhibition. Main features for the readout Analog OR of the 72 discriminator outputs [1 current output].Analog OR of the 72 discriminator outputs [1 current output]. Address of the hit channel (through slow control link).Address of the hit channel (through slow control link). 4 SCA readout modes.4 SCA readout modes. [AD9229] Slow ControlSlow Control Power on resetPower on reset Test mode:Test mode: calibration or test [channel/channel] functional [72 channels in one step] Spy mode on channel 1:Spy mode on channel 1: CSA out, PZC out, FILTER out or DISCRI in.

3. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 3 AFTER+: Mode of operation Discri_in Discri_out Hit_channel Trigger_out Write_SCA Read_Address_hit channel Reset Read_SCA Data_SCA_outSCA_in Channel i Stop Sampling: on external or local Trigger SCA write address read SCA read SCA write CSA_in

4. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 4 AFTER+: SCA SCA Manager SCA write 76 lines 511 cells SCA read Clk write Clk read R Vreturn:0,7V In Bufferout W Analog Memory: 72 channels + 4 dummy channels [for common mode or Fix pattern noise rejection purpose]. Write: 1MHz to 100MHzWrite: 1MHz to 100MHz Read: 20MHzRead: 20MHz Dynamic: 1.5V (full range)Dynamic: 1.5V (full range) Clock: LVDSClock: LVDS Mode (W & R): CMOSMode (W & R): CMOS CLKwrite CLKread Write Read Write phase Read phase

5. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 5 AFTER+: SCA Write Phase Fsampling: 1MHz to 100MHz.Fsampling: 1MHz to 100MHz. Peaking Time: 50ns to 1µs (16 values).Peaking Time: 50ns to 1µs (16 values). 511 cells SCAFILTER tpeak CSA channel Cf DAC Discri PAD x y z particle z0 z1 T z=z0 t trigger T z=z1 t trigger – t z=z0 ≤ 511 / F sampling t 0= arrival time Time z max L drift pad T z=zmax t driftzmax t driftz1 t driftz0 c0 c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 Architecture : circular memory Sampling condition : 511x(1/Fsampling) ≥ Tdriftmax Peaking Time : Tpeak ≥ N x (1/Fsampling)

6. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 6 c0 c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0 c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 AFTER+: SCA Read Phase Channel Readout mode : all channels; hit channels or specific channels Readout Time: 511 x [n channel + 3] x Trck + 79 x Trck = 80.6 µs + 25.55 µs x nchannel [Trck = 50 ns]. n = 1 channel => Readout time = 106.15 µs.. n = 10 channels => Readout time = 336.1 µs.. n = 36 channels => Readout time = 1 ms.. n = 76 channels => Readout time = 2.022 ms. c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 c0c510 c509 ci-2 c1 c. ci ci-1 ci+1 ci+2 Column n Channel 0 Channel 2 Channel n Channel 75

7. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 7 AFTER+: SCA Read Phase Hit or specific channels: Slow control serial link & hit channel register (72 bits) Readout of the hit channel address idle X 1 ADD XXXXX Address r/wb=1=> read Y idle Sc_din Sc_ck Sc_en Sc_dout 8.5xTck:425ns 72xTck:3.6µs Write_SCA Read_address_hit channel Clear Read_SCA Write_address_read channel idle X 0 ADD Address Data r/wb=0=> write idle Sc_din Sc_ck Sc_en Sc_dout 7.5xTck:375ns 72xTck:3.6µs XXXXX Write of the readout channel address

8. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 8 AFTER+: SCA Read Phase SCA readout mode: 511, 256 or 128 analog memory cells / channel Write phase: Tdrift ≤ 511 / Fsampling Read phase: SCAcells = 511 0 510 Stop (trigger) Readout phase Write phase: 2 x Tdrift ≤ 511 / Fsampling Read phase: SCAcells = 256 0 510 Stop (trigger) Readout phase Write phase: 4 x Tdrift ≤ 511 / Fsampling Read phase: SCAcells = 128 0 510 Stop (trigger) Readout phase 511 analog memory cells / channel:511 analog memory cells / channel: ci ci+1 ci 256 analog memory cells / channel:256 analog memory cells / channel: 128 analog memory cells / channel:128 analog memory cells / channel: InternalLogicalOperation Write phase

9. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 9 4-bit DAC AFTER+: Threshold channel Architecture: L.E.D + DAC (4 bits/channel + 3 bits/72 channels) FILTER Analog out CSA 1 channel Discri PZC G2 + - Sign Polarity Memory Hit Channel 511 cells SCA Inhibit Gain OR_hit channel I in I=I in Hit channel 01 I in I=I in Hit channel 02 I in I=I in Hit channel i I in I=I in Hit channel 72 72 x Iin Slow Control Register (2 bits) I in 3-bit DAC Trigger output: analog OR of the 72 hit channel registers. Need specifications: -Current value -Rise & Fall time -Rout&Cout -Linearity (72*Iin ??)

10. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 10 AFTER+: Architecture of the test system 3 test modes: Test, Functionality & Calibration Calibration: Charge injected channel by channel (selection 1/72 channel by Slow Control). selj seli x72 Pulse Generator ASIC Functionality of the global electronic system: Charge injected on all channels (or a part), at the same time. [in this mode, the FPN channels can be tested] Pulse Generator selj seli x76 ASIC Test: Charge injected channel by channel (selection 1/72 channel by Slow Control). [1 internal injection capacitor/charge range] selj seli x72 Pulse Generator ASIC X3 (1/Charge range) Ccali

11. ACTAR WORKSHOP Bordeaux (CENBG) June 17, 2008 11 AFTER+: Requirements ParameterValue Polarity of detector signalNegative or Positive Number of channels72 External PreamplifierYes; access to the filter or SCA inputs Charge measurement Input dynamic range120 fC; 1 pC; 10 pC GainAdjustable/(channel) Output dynamic range2V p-p I.N.L< 2% Resolution< 850 e- (Charge range: 120fC; Peaking Time: 200ns; Cinchannel. < 30pF) Sampling Peaking time value50 ns to 1 µs (16 values) Number of SCA Time bins511 Sampling Frequency1 MHz to 100 MHz Time resolution Jitter60 ps rms Skew< 700 ps rms Trigger Discriminator solutionL.E.D Trigger Output/MultiplicityOR of the 72 hit channel registers; Current output Dynamic range5% of input charge range I.N.L< 5% Threshold value4-bit DAC/channel + (3-bit + polarity bit) common DAC Minimum threshold value≥ noise Readout Readout frequency20 MHz to 25 MHz Channel Readout modeHit channel; specific channels; all channels SCA Readout mode511 cells; 256 cells; 128 cells Test calibration1 channel / 72; external test capacitor test1 channel / 72; internal test capacitor (1/charge range) functional1, few or 76 channels; internal test capacitor/channel Counting rate< 1 kHz Power consumption< 10 mW / channel