1. 1 1 JEITA STD-TSC updates JEITA EDA standardization subcommittee, Vice chair IEC TC93 WG2, Co-convener NECST CWB business division, Director Satoshi Kojima IEEE-DASC meeting at EDSFair2009, Yokohama 8:30 -10:00, 23 rd January 2009 (JST) CM4 room at Pacifico Yokohama

2. 2 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Introduction   Who joins a meeting from Yokohama   Organization chart and updates of STD-TSC and WGs Some concerns on DASC activities   SystemC TLM2.0 LRM hand-off from OSCI   Power Format 1801 balloting results and future actions   Sensibility SPEF status of P1481   AMS harmonization among three AMS languages Summary Summary - Outline -

3. 3 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Attendees : Victor Berman: DASC Chair, TC93 Secretary, Improv Systems Stan Krolikoski: DASC Vice-chair, OSCI Treasurer, Cadence Dennis Brophy: Accellera Vice-chair, TC93 WG2 Co-convener, Mentor Satoshi Kojima: JEITA STD-TSC Vice-chair, WG2 Co-convener, NECST (Guests) Ohta-san: JEITA STD-TSC Chair, Panasonic, Hasegawa-san: SystemC WG Chair, Fujitsu Microelectronics Hamaguchi-san: System Verilog WG Chair, Panasonic Nakamori-san: Power Format WG Chair, Fujitsu Microelectronics Kanamoto-san: Nano-scale Physical Design WG Chair, Renesas Technology Yamamoto-san: Oki semiconductor, Furui-san: STARC Tanaka-san: Panasonic, Hachiya-san: JEDAT and Takafuji-san: Richo Who joins a meeting from Yokohama

4. 4 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA JEITA Structure and Management Japan Electronics and Information Technology Industries Association JEITA Policy and Strategy Board Environment Board Consumer Electronics Board IT and Industrial Systems Board Display Devices Board Electronic Components Board Semiconductor Board (JEITA-JSIA) Semiconductor Industrial Affairs Committee Semiconductor International Affairs Committee Semiconductor Technology Committee Marketing Committee Road Map Committee EDA Technical Committee (EDA-TC) - - Member : 21 Companies Fujitsu ML, Panasonic, NEC EL, Toshiba, Renesas, Sanyo, Sharp, Sony, Rohm, Seiko Epson, Synopsys, Toppan, Cadence, JEDAT, Mentor, Ricoh, Zuken, Marubeni.Sol, Magma, CoWare and HDLab Full Member : 366 companies Associate Member : 150 companies

5. 5 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA EDA-TC Structure in fiscal year 2008 EDA Technical Committee EDA Standardization Technical Sub-Committee SystemC Working Group SystemVerilog Working Group NPD(Nano-scale Physical Design) Working Group EDSFair 2009 Executive Committee Acceleration of Standardization Solution for Technical Challenges Promotion of EDA Technology Chair: T.Yamada (SANYO) Chair : K.Kawamura (Fujitsu ML) Chair: T.Kanamoto (Renesas) Chair : M.Ohta (Panasonic), Vice-chair : T.Eda (Rohm) S.Kojima (NEC-ST) Chair : T.Hasegawa (Fujitsu ML) Chair : K.Hamaguchi (Panasonic) Power Format Working Group Chair : T.Nakamori (Fujitsu ML)

6. 6 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Member: 23 members from Semiconductor vendors, EDA vendors and academia   Chair: M.Ohta (Panasonic)   Vice-chairs: T.Eda (Rohm), S.Kojima (NECST) To reflect opinions on technical and business issues as a group of EDA power users to De Jure standard bodies such as IEEE and IEC TC93 To raise issues on design flows to solve today and future design issues from the member companies and to propose what standard can contribute to solve them Three subsidiaries are actively working on   SystemC Working Group   SystemVerilog Working Group   Power Format Working Group EDA Standardization TSC Activities

7. 7 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Collaboration w/IEEE and IEC Domestic collaboration   To dispatch a chair and some experts to WG2 of IEC TC93 JNC in IEICE (The Institute of Electronics, Information and Communication Engineers) and to lead the activities of the WG2 JNC Global collaboration   Worked with P1800WG (SystemVerilog), P1666WG (SystemC) and P1801WG (Power format) in IEEE-DASC, reviewing the drafts and participating in the balloting. Planning work with P1481(SSPEF)   Has been a member of IEEE-SA since 2004 and participated in balloting such as IEEE1800, IEEE1666 in 2005 and IEEE1801 in 2008   Kojima has been a Co-convener of TC93 WG2 since 2000 and works with Dennis Brophy in USNC   IEEE-IEC Dual Logo agreement made in 2003 accelerates EDA global standardization and expanded beyond TC93 in 2008

8. 8 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA IEICE TC93 JNC JEITA EDA STD-TSC WG2 JNC IEEE IEEE-SA IEC TC93 Int’l WG1,WG2… Accellera, OSCI WG2 JNC EDA-TC WGs (P1666, P1800, P1801, …) DASC CAG NesCom, RevCom SC-WG SV-WG PF-WG Association member Hand-offs from feeder org. Collaboration Collaboration scheme Dual Logo agreement Representatives

9. 9 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Nano-scale physical design WG Activities To investigate technical issues on physical design. Has just started Sensitivity SPEF activities Member : Experts from 12 companies and academia   Chair: T.Kanamoto (Renesas)   Renesas, NEC EL, Oki, Sanyo, Ricoh, JEDAT, Panasonic, Fujitsu ML, STARC, Osaka Univ. and Tokyo IT Current activities:   Leakage current variation   Self-heating impacts in wires on delay variation

10. 10 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA SystemC-WG Activities To standardize design language and its subsidiaries of synthesis and verification to support ESL design methodology Member : Experts from 13 Companies   Chair: T.Hasegawa (Fujitsu ML)   Cadence, Fujitsu ML, Panasonic, Mentor, NEC EL, Oki, Renesas, Sanyo, Sony, Synopsys, Toshiba, NECST Past outcomes since Oct. 2003:   Contributed to IEEE Std. 1666-2005 (Dec, 2005) as a voting member   Developed the outline of the Coding Style Guideline for HL Synthesis   Develop a HL Synthesis part of “Recommended design methodology” Current activities: Contribution standardization activity of TLM 2.0 (Review OSCI’s documents, and submitted issue reports to OSCI) Sponsor the annual Japan SystemC User’s Forum 2005 thru 2008 in conjunction with the EDSF at Yokohama Has continued to develop “Recommended design methodology” to fulfill some parts such as verification, SW design, Modeling for simulation efficiency….

11. 11 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA SystemVerilog WG Activities To standardize verification language to support new methods such as constrained random, assertion-based and coverage- driven verification Member : Experts from10 Companies   Chair: K.Hamaguchi (Panasonic)   Cadence, Fujitsu, Panasonic, Mentor, Oki network LSI, Renesas, Sanyo, Synopsys, Toshiba, Zuken Joined IEEE P1800-WG as a voting member, and Contributed to IEEE Std. 1800-2005 (Nov. 2005) :   Over 32 issues/requests through reviews has almost adopted Join IEEE P1800-2010 WG (Integration of VerilogHDL and SystemVerilog) to review the draft, and will participate in an upcoming balloting in Jan 2009   Submitted 35 issues in May 2007 and Re-submitted in Nov. 2007   Confirmed all requests to be adopted

12. 12 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Power Format WG Activities To standardize format to manage overall low power design processes Member : Experts on low power design from 7 Companies   Chair: T.Nakamori (Fujitsu)   Fujitsu, Matsushita, SONY, Renesas, Sanyo, Toshiba, SEIKO EPSON Study capabilities of two forum standards, UPF and CPF, from a viewpoint of practical SoC design flows since Oct. 2007 Complete UPF vs. CPF comparison table   Scope: Multi-voltage and Shut-off mechanism   Priority: #1=Verification and Synthesis, #2=Library, Formal and Rule Check   To clarify the difference of two formats To review a final draft and joined an IEEE 1801 balloting in Nov 2008   Did negative ballot to attach 13 issues report   4 agrees, 6 disagrees and 3 principles after negative resolution

13. 13 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Introduction   Who joins a meeting from JEITA   Organization chart and updates of STD-TSC and WGs Some concerns on DASC activities   SystemC TLM2.0 LRM hand-off from OSCI   Power Format 1801 balloting results and future actions   Sensibility SPEF status of P1481   AMS harmonization among three AMS languages Summary Summary - Outline -

14. 14 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Some concerns on DASC activities SystemC TLM2.0 LRM hand-off from OSCI   Let us know key target milestones for IEEE standard such as LRM hand-off to OSCI, WG formation, balloting… Power Format 1801 balloting results and future actions   Did negative ballot to attach 13 issues report   Classified into 4 agrees, 6 disagrees and 3 principles after negative resolution   Did not change our attitude, still negative   What is going on P1801?

15. 15 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Introduction   Who joins a meeting from JEITA   Organization chart and updates of STD-TSC and WGs Some concerns on DASC activities   SystemC TLM2.0 LRM hand-off from OSCI   Power Format 1801 balloting results and future actions   Sensibility SPEF status of P1481   AMS harmonization among three AMS languages Summary Summary - Outline -

16. 16 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Overview Predicting problems when SSPEF is applied to LSI design Considering methods of solving problems and enhancing Sensitivity SPEF if needed From the viewpoint of Accuracy From the viewpoint of EDA tool ’ s run time Issues on the table VARIATION_PARAMETERS is only defined by proportion or inverse proportion. SSPEF doesn't include On-chip random variation or correlation factors, such as correlation between layers. metal2 metal1 T1 H1 T2 H2 -3σ +3σ C T -3σ +3σ R -1 T SSPEF model Physical model On-chip random variation R Net (i) Planning on Sensitivity SPEF activities

17. 17 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Who (or which company) is participating in Sensitivity SPEF standard activity/meeting? How often the meeting is held? Which EDA tools can handle SSPEF at present? When we have to consider wire dimension variation in Statistical STA? Do you have trend prediction of variation increase of wire dimension and its impact on path delay variation? Do you think wire delay variation is not negligible for short wires (shorter than repeater insertion criteria) ? Request on participation P1481

18. 18 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Introduction   Who joins a meeting from JEITA   Organization chart and updates of STD-TSC and WGs Some concerns on DASC activities   SystemC TLM2.0 LRM hand-off from OSCI   Power Format 1801 balloting results and future actions   Sensibility SPEF status of P1481   AMS harmonization among three AMS languages Summary Summary - Outline -

19. 19 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA AMS languages harmonization An AMS language is derived from a digital design language to cover digital- analog mixed signal world In result, there are three AMS languages in an EDA community   VHDL-AMS is IEEE standard and might be in an academia   Verilog-AMS might be De Facto standard in the market   SystemC-AMS will be OSCI standard soon JEITA had some good lessons-learned through power format standardization activities under 2 formats issues of UPF and CPF   Criteria to qualify De Jure standard is applicable for practical SoC design flow or not   Unification is best, but in reality interoperability and/or harmonization are indispensable How does DASC think to deal w/AMS language harmonization? JEITA is planning to set strategies to deal w/existing standards and emerging standards

20. 20 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA EDA standards provide a mechanism for defining common semantics for integrated design systems among various tools To define common SoC design flow and then categorize existing standards and emerging ones To set strategies of EDA standardization activities for every category JEITA to set strategies of EDA standards System Design Specification (Function + Constraints) Analyze Implement w/Opt. Equivalence check Circuit Logic Software Scan/BIST Place Route DFM DFT Noise Power Timing Area Communicate Libraries Verification Data for manufacturing Testability Performance Function

21. 21 Copyright(C) JEITA 2008 IEEE-DASC Yokohama meeting, 23Jan2009© Copyright 2009 JEITA Summary To update JEITA standardization activities such as STD-TSC, SystemC WG, System Verilog WG, Power Format WG and Nano-scale physical design WG To talk about some concerns on DASC activities SystemC TLM2.0 Power Format balloting Sensitivity SPEF AMS language harmonization

22. 22 JEITA : Japan Electronics and Information Technology Industries Association ( URL http://www.jeita.or.jp) EDA-TC : EDA Technical Committee ( URL http://eda.ics.es.osaka-u.ac.jp/jeita/eda/index.html)