1. XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing

2. 2 18 February 2010C+C μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout FEE 5MHz Clock Trigger + Telegram ID Bunch Veto 4 FEE 4 C+C Fanout Slave XFEL Timing Interface Other 1-20MHz? Clock Trig/Data Overview MINIMUM FANOUT REQUIREMENTS : 16 + Fanouts, expandable 3x Outputs ( diff. LVDS, STP/UTP ) 1x Input ( single line, level only )

3. 3 18 February 2010C+C Fast Commands -1- Three Fast Command Lines : - Fanned out to all FEEs via C&C Fan-outs -Same cable lengths -No individual adjustable delays - AC coupling on FEEs : ANALOG ADuM3441 ( 3+1 ) magnetic BUT : Max. skew : 2ns/channel, 12ns/device => prog. delays BUT : Max. skew : 2ns/channel, 12ns/device => prog. delays 1) ~100 MHz CLOCK : IF 4.5 MHz bunch clock => 99 MHz 1) ~100 MHz CLOCK : IF 4.5 MHz bunch clock => 99 MHz Integer multiple of the incoming ~5 MHz clock from T.R. Integer multiple of the incoming ~5 MHz clock from T.R. PLL-ed to the incoming 5 MHz clock ( 20x / 22x ) PLL-ed to the incoming 5 MHz clock ( 20x / 22x ) Un-interrupted Un-interrupted Fixed phase relationship to the 5 MHz clock Fixed phase relationship to the 5 MHz clock

4. 4 18 February 2010C+C Fast Commands -2- 2A) START-TRAIN / TRAIN-ID / BUNCH-STRUCTURE-ID / STOP 2A) START-TRAIN / TRAIN-ID / BUNCH-STRUCTURE-ID / STOP Synchronised to the 100 MHz clock Synchronised to the 100 MHz clock Fixed phase relationship to the 5 MHz clock Fixed phase relationship to the 5 MHz clock a) START : 1100 = 4 bits a) START : 1100 = 4 bits Start pulse to start about ~ 15 msec ( programmable in Start pulse to start about ~ 15 msec ( programmable in 200 nsec steps ) before the train arrives 200 nsec steps ) before the train arrives b) TRAIN-ID : = 32 bits b) TRAIN-ID : = 32 bits The train number is a unique number. From the DAQ point of The train number is a unique number. From the DAQ point of view it should never repeat and should continuously count up view it should never repeat and should continuously count up GPS time NOT USED ??? Generated on C&C ( counter ? ) ?? GPS time NOT USED ??? Generated on C&C ( counter ? ) ?? - Does this include Trigger Type NO – SOFTWARE ONLY - Does this include Trigger Type NO – SOFTWARE ONLY

5. 5 18 February 2010C+C Fast Commands -3- c) BUNCH-STRUCTURE-ID : = 8 bits MAX c) BUNCH-STRUCTURE-ID : = 8 bits MAX probably only ~16 patterns for any given run/day probably only ~16 patterns for any given run/day d) CheckSum of b) and c) = 8 bits MAX d) CheckSum of b) and c) = 8 bits MAX - Assume maximum 3000 bunches per train e) STOP : 1010 = 4 bits e) STOP : 1010 = 4 bits Stop pulse at the END OF THE TRAIN Stop pulse at the END OF THE TRAIN

6. 6 18 February 2010C+C Additional Fast Commands -3B- 2B) RESET uC : 1001 = 4 bits to reset the FE micro-controller via the FE FPGA to reset the FE micro-controller via the FE FPGA 2C) Reserved : 1111 = 4 bits

7. 7 18 February 2010C+C Fast Commands -4- 3A) VETO BUNCH : ??? Synchronised to the 100 MHz clock Synchronised to the 100 MHz clock Adjustable phase relationship to the 5 MHz clock : YES Adjustable phase relationship to the 5 MHz clock : YES ( up-to 10 clocks for LPD ) ( up-to 10 clocks for LPD ) a) VETO FOLLOWS command : 110 = 3 bits a) VETO FOLLOWS command : 110 = 3 bits b) BUNCH-ID : = 12 bits b) BUNCH-ID : = 12 bits c) -reserved- : = < 5 bits ??? c) -reserved- : = < 5 bits ??? 3B) NO VETO ??? a) NO-VETO-FOLLOWS command : 101 = 3 bits a) NO-VETO-FOLLOWS command : 101 = 3 bits b) BUNCH-ID : = 12 bits b) BUNCH-ID : = 12 bits c) -reserved- : = < 5 bits ??? c) -reserved- : = < 5 bits ???

8. 8 18 February 2010C+C Fast Commands -5- 1) ~100 MHz CLOCK 2A) START-TRAIN / TRAIN-ID / BUNCH-STRUCTURE-ID / STOP a) START : 1100 = 4 bits } a) START : 1100 = 4 bits } b) TRAIN-ID = 32 bits } ~52 bits => b) TRAIN-ID = 32 bits } ~52 bits => c) BUNCH-STRUCTURE-ID = 8 bits } 520 nsec max c) BUNCH-STRUCTURE-ID = 8 bits } 520 nsec max d) CheckSum = 8 bits } d) CheckSum = 8 bits } e) STOP : 1010 = 4 bits e) STOP : 1010 = 4 bits 2B) RESET uC : 1001 = 4 bits 2C) - Reserved - : 1111 = 4 bits

9. 9 18 February 2010C+C Fast Commands -5B- 3A) VETO BUNCH a) VETO FOLLOWS Command : 110 = 3 bits a) VETO FOLLOWS Command : 110 = 3 bits b) BUNCH-ID = 12 bits b) BUNCH-ID = 12 bits c) -reserved- = < 5 bits ??? c) -reserved- = < 5 bits ??? 3B) NO VETO ??? a) NO-VETO-FOLLOWS command : 101 = 3 bits a) NO-VETO-FOLLOWS command : 101 = 3 bits b) BUNCH-ID : = 12 bits b) BUNCH-ID : = 12 bits c) -reserved- : = < 5 bits ??? c) -reserved- : = < 5 bits ???

10. 10 18 February 2010C+C FEs Status Feedback STATUS FEEDBACK from all FEEs :STATUS FEEDBACK from all FEEs : Each FEE plugged-in & powered-up Each FEE plugged-in & powered-up Status only : OK = ?? MHz clock Status only : OK = ?? MHz clock ERROR = high / low / floating... ERROR = high / low / floating...

11. 11 18 February 2010C+C Network Messages from C&C - RUN CONFIGURATION Received from T.R. via backplane / software Received from T.R. via backplane / software

12. 12 18 February 2010C+C Questions -1- :

13. 13 18 February 2010C+C Veto Unit Questions / Comments -2- Presume 5 MHz Clock and Train-Start ( ? ) are common to Veto Detector and to Veto Unit 2 scenarios : 1)Veto sent synchronous to bunch it vetoes Dont need to decode bunch-id bits if fast enough Synchronised to 5MHz No start-bits etc for serialised bunch-id Inputs bunch/train phase aligned using delays Synchronised to 100 MHz clock 10ns steps for bunch alignment ( ? ) Single bunch-id counter used on all inputs Time-in one input using common Train-Start or Test-Veto signal HOW ?? Veto Detector sends veto on bunch 0 VU counts delay/offset between Train-Start / Test-Veto and Veto-0 Can time in all other inputs to first one Note : At some point proper timing in with a single bunch will need to be done …

14. 14 18 February 2010C+C C&C Crate TB Crate FEE ARM CPU / Network messaging Summarise our understanding of the system : Control in centralised, but not on the C&C PC C&C PC takes care of requesting/accepting/fetching info from C&C Card/s This includes snapshots and train info from TR DAQ PC requests/accepts/fetches info from C&C PC C&C Card communicates with FEE FPGA Outstanding Questions : Should the C&C have a command for resetting the FEE uC : YES !! The doc implied the FEE requesting a snapshot from C&C – really ?? DAQ PC C&C PC TB PC C&C Card FEE FPGA FEE uC TB Card

15. 15 18 February 2010C+C Fanout 8 TCP/ IP Local AMC Control To FEE FPGA TR / Machine etc. Signals or inputs from C&C Master Outputs to Fanouts c) Single integrated card Master PLL etc

16. 16 18 February 2010C+C End…..