Presentation is loading. Please wait.

Presentation is loading. Please wait.

Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no.

Published byIsabel Lyon Modified over 10 years ago

Similar presentations

Presentation on theme: "Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no."— Presentation transcript:

1 Thoughts on C&C hardware modularity

2 Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no need for custom backplane as all boards will have communication built-in MTCA Slave is a bit of a waste of all this... Maybe something more modular … –Generic baseboard with plugins –Master = 1x fanout + 1x TR/beam interfaces plug-in –Slave = 2x fanout

3 TCP/IP Local AMC Control Fanout 8 Plug-in CC Master To FEE FPGA Master Plug-in TR/ Machine etc. Signals PLL etc Vertical Plugins (double stack conn.)

4 Layered plugins (single stack conn.) TCP/IP Local AMC Control Fanout 8 Plug-in To TR or CC Master To FEE FPGA Master Plug-in PLL etc

5 More Thoughts Multiple plug-ins nice as all fanouts are equal (delays etc.) BUT a C&C baseboard with 8x fanout integrated has other advantages: –Basic unit of the C&C system is one board –Cheaper Maybe play the same PCB but load only the parts required … –Larger FPGA (more logic/IO) on Master

Download ppt "Thoughts on C&C hardware modularity. Concept Master and Slave will be proper AMC AMC boards will be fairly smart: Micro-controller Small FPGA? –So no."

Similar presentations

XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 4 December 2008 Martin Postranecky Matt Warren, Matthew Wing.
XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.

XFEL C+C HARDWARE : REQUIREMENTS 1) To receive, process and store Timing Signals from TR ( Timing Receiver ) in same crate : - 5 MHz Bunch CLOCK - Bunch.
Μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout Slave FEE 5MHz Clock Trigger.

Μ TCA Crate Timing Receiver Crate Processor 100 MHz Clock Start/Info/Stop Bunch Veto FEE Status C+C Master FEE C+C Fanout Slave FEE 5MHz Clock Trigger.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 22 October 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 23 April 2009 Martin Postranecky Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, DESY 18 February 2010 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System Train Builder Meeting, MANNHEIM 02 July 2009 Martin Postranecky, Matt Warren, Matthew Wing.

XFEL 2D Pixel Clock and Control System Train Builder Meeting, MANNHEIM 02 July 2009 Martin Postranecky, Matt Warren, Matthew Wing.
XFEL 2D Pixel Clock and Control System. 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware.

XFEL 2D Pixel Clock and Control System. 2 OUTLINE June meeting at DESY June meeting at DESY C&C Hardware structure C&C Hardware structure C&C Firmware.
XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.

XFEL Meeting, Hamburg September 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.
New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.

New Corporate Identity Poster Design Department of Physics and Astronomy, University College London Erdem Motuk, Martin Postranecky, Matthew Warren, Matthew.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.

1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.
RLH - Spring 1998ECE 611 Hardware - 1 Basic Microprocessor Hardware ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department.

RLH - Spring 1998ECE 611 Hardware - 1 Basic Microprocessor Hardware ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department.
Clock module for TB spring 2012 Uli Schäfer 1 R.Degele, P.Kiese, U.Schäfer, A.Welker Mainz.

Clock module for TB spring 2012 Uli Schäfer 1 R.Degele, P.Kiese, U.Schäfer, A.Welker Mainz.
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design N. Vinay Krishnan EE249 Class Presentation.

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design N. Vinay Krishnan EE249 Class Presentation.
Week 1- Fall 2009 Dr. Kimberly E. Newman University of Colorado.

Week 1- Fall 2009 Dr. Kimberly E. Newman University of Colorado.
Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.

Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.
Hardware status GOLD Update 02 Feb. 2010 Uli Schäfer 1.

Hardware status GOLD Update 02 Feb Uli Schäfer 1.
11/18/2004Comp 120 Fall 20041 18 November 3 classes to go No class on Tuesday 23 November Last 2 classes will be survey and exam review Interconnect and.

11/18/2004Comp 120 Fall November 3 classes to go No class on Tuesday 23 November Last 2 classes will be survey and exam review Interconnect and.

Similar presentations

Ads by Google