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XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System.

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Presentation on theme: "XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System."— Presentation transcript:

1 XFEL Meeting, RAL 20 January 2011 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing XFEL 2D Pixel Clock and Control System

2 2 OUTLINE Progress up to date Progress up to date Hardware Structure Hardware Structure Firmware structure Firmware structure Current Status Current Status Outstanding Issues Outstanding Issues Future plans Future plans

3 3 Progress up to date Acquired software and licence for Allegro ConceptHDL Acquired software and licence for Allegro ConceptHDL – Design flow established – The first run slightly slow – improved for others – Schematic design and packaging at UCL – Layout at RAL Test card A design Test card A design – Schematic entry/layout finished – Named PC3461M – In the manufacturing and assembly stage RTM design has started RTM design has started – Schematic entry started xTCA crate has been purchased xTCA crate has been purchased – Set up and running with SLC

4 4 Progress up to date Firmware design on the development platform Firmware design on the development platform – Telegram transmit/receive – FAST message transmit/receive – Test Bench Firmware comprising all transmit/receive blocks Firmware comprising all transmit/receive blocks Transmit can be started by external input (push-button or ChipScope VIO) Transmit can be started by external input (push-button or ChipScope VIO) Results can be observed by ChipScope Results can be observed by ChipScope – PCIe Development card can be accessed through PCIe Development card can be accessed through PCIe – Manual start/stop (standalone operation)

5 5 Hardware Structure PCM3461 Assembly drawing top and bottom sides RECEIVE TRANSMIT Test / Prototyping area

6 6 Hardware Structure PC3461M to be used for PC3461M to be used for – FAST message transmit/receive testing (via ETH cables) – Telegram message transmit/receive testing – Available for others to use (with the XUPV5 development board)

7 7 Hardware Structure Prototype RTM to test with the DAMC2 board in the xTCA crate Prototype RTM to test with the DAMC2 board in the xTCA crate – Early prototype availability for the system – Diagnosing bugs/gotchas with the design – Later revision to add more capability – Prototyping platform for extra features if needed for extra features if needed – Tests to be carried out in the actual setup (xTCA crate) in the actual setup (xTCA crate) RJ45 CONNECTORS (8/16) LVDS DRIVERS LVDS RECEIVE CLOCK / PLL I2C / EEPROM POWER

8 8 Firmware Structure A test firmware that integrates transmit/receive and other features A test firmware that integrates transmit/receive and other features – One bit file to program the FPGAs on the dev boards – ChipScope cores associated with each block Firmware diagram – Finished blocks + extras for test Firmware diagram – Finished blocks + extras for test Clocking implemented according to the dev board Fast Message Receive implemented as a part of LPD FEM firmware Telegram transmit implemented for TR Buttons on dev board

9 9 Telegram transmit/receive Telegram transmit/receive Two packet structures for data and events Start Byte (x2C) + Write_Type + CRC (for events) Start Byte (x2C) + Write_Type + CRC (for events) Start Byte (x2C) + Write_Type + Data (32-bit) + CRC (for data) Start Byte (x2C) + Write_Type + Data (32-bit) + CRC (for data) WR_CLK can be different than 108 MHz ASYNC FIFO in the transmitter ASYNC FIFO in the transmitter FLAG_OUT indicates types of events and data 8-bit CRC IDLE pattern (x5885) sent between packets Firmware Structure BUNCH_PAT_ID TRAIN_NO_OUT FLAG_OUT (event/data) CLK_OUT (27 MHz) TEL_CLK_OUT TEL_DATA_OUT CLK108 WR_TYPE WR_DATA WRITE_CLK WR_EN TRANSMIT RECEIVE TRCC SIGNAL DIAGRAM FOR TRANSMIT INPUT

10 10 Firmware Structure REG_HIT_ACK REG_INPUT REG_HIT CLK_OUT DATA_OUT RECEIVE RESET START END_TRAIN BUNCH_PAT_ID TRAIN_NO_OUT BUNCH_PAT_ID TRAIN_NO_OUT FLAG_OUT (event/data) CLK_OUT (27 MHz) REGISTERS FAST TX PCIE EXT TRIG PCIe block Xilinxs Virtex5 embedded PCIeBlockPlus core Xilinxs Virtex5 embedded PCIeBlockPlus core Programmable memory read/write functionality in firmware Programmable memory read/write functionality in firmware A simple driver written for Linux A simple driver written for Linux A simple application to access registers on the FPGA A simple application to access registers on the FPGA To read/write Train_no and Bunch_Pattern_Id To read/write Train_no and Bunch_Pattern_Id

11 11 Firmware Structure Fast Message Transmit Implemented according to the specs Implemented according to the specs Simple XOR checksum Simple XOR checksum Register block Register block Different registers for different sources Different registers for different sources – PCIe and telegram data at the moment Multiplexes between different sources for FAST message transmit Multiplexes between different sources for FAST message transmit External Trigger Buttons on the board Buttons on the board Start / Stop / Reset Start / Stop / Reset

12 12 Current Status C&C firmware C&C firmware – Fast Message Generation – Start and Stop messages – Telegram receive

13 13 Current Status

14 14 Current Status TEST SETUP

15 15 Outstanding Issues – Telegram transmit/receive testing and feedback Further development / debugging Further development / debugging – RTM design Exact dimensions of the RTM card Exact dimensions of the RTM card DAMC2 schematic or a manual needed DAMC2 schematic or a manual needed Any experience / useful to know bits Any experience / useful to know bits – TR and DAMC2 availability – xTCA crate Operating system / device drivers Operating system / device drivers Any gotchas / experience with the crate Any gotchas / experience with the crate

16 16 Schedule PC3461M ready PC3461M ready – Initial testing with the card – Card made available RTM design RTM design – Schematic capture – Layout – Manufacturing Further firmware debug / development Further firmware debug / development – With the DAMC2 board – With the TR board – In the xTCA crate – VETO logic February 2011 March 2011 February 2011 March 2011 April 2011 February – April 2011

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