1. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 A Combined Clustering and Placement Algorithm for FPGAs Mark Yamashita

2. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 2 Contributions New algorithm to do clustering and placement Novel approach for trading-off depth for duplication control Timing model/placement incorporated into clustering Delay improves by an average of 11% Controllable trade-off between area overhead and delay improvements Plan to submit to FPL ‘08

3. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 3 Motivation FPGAs need to be faster 4x slower than ASICs Limitations of existing clustering approaches: No depth control during clustering, often greedy Provide no means for duplication, or Use duplication in excess Inaccurate timing models

4. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 4 Motivation GOAL: Improve critical-path delay by improving clustering Approach: Use placement information to form accurate timing model Make better clustering decisions Use duplication to reduce depth Take advantage of otherwise unused logic in FPGA Control amount of duplication by relaxing depth

5. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 5 Algorithm Overview T-VP

6. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 6 Phase 1: Microcluster Formation

7. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 7 Phase 1: Example

8. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 8 Phase 1: Lawler Levitt Turner Algorithm

9. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 9 Phase 1

10. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 10 Phase 1: Node Duplication Reduction

11. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 11 Phase 1: Block Usage Results

12. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 12 Phase 1: Additional Duplication Reduction Through Depth Relaxation

13. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 13 Algorithm Overview T-VP

14. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 14 Phase 2: Microcluster Compaction with Orchestrator Iteratively move microclusters to improve timing Can fit multiple microclusters to the same CLB position, provided the aggregate of all microclusters meets CLB constraints If an area constraint is given, remove duplication and fragmentation until constraint is met

15. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 15 Phase 2: Orchestrator Example

16. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 16 Phase 2: Orchestrator Example

17. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 17 Phase 2: Orchestrator Example

18. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 18 Phase 2: Orchestrator Example

19. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 19 Phase 2: Orchestrator Example

20. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 20 Phase 2: Orchestrator Example

21. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 21 Phase 2: Orchestrator Example

22. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 22 Results: Timing

23. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 23 Results: Area

24. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 24 Results: Timing vs. Area

25. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 25 Results: Timing vs. Depth

26. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 26 Conclusions Reducing depth contributes to a reduction in critical path delay Node duplication, when used effectively, reduces critical path delay Duplication can be used to provide a performance-area tradeoff to the designer

27. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 27 Future Work Promising Post-Placement Optimizations: Retiming Leverage a more significant depth reduction Logic reintroduction Create duplication to increase performance

28. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 28 Contributions New algorithm to do clustering and placement Novel approach for trading-off depth for duplication control Timing model/placement incorporated into clustering Delay improves by an average of 11% Controllable trade-off between area overhead and delay improvements Plan to submit to FPL ‘08

29. University of British Columbia Dept. of Electrical and Computer Engineering November 30, 2007 29 Thank You