1. HFT PIXEL Detector Pre-practice CDR-1 Review 3-Sept.-2009 Wieman 1

2. Topics Pixel detector system requirements and properties detector chip and readout development Mechanical development 2

3. Pixel geometry. These inner two layers provide the projection precision 2.5 cm radius 8 cm radius Inner layer Outer layer End view One of two half cylinders 20 cm  coverage +-1 total 40 ladders

4. 4 Some pixel features and specifications Pointing resolution(13  22GeV/p  c)  m LayersLayer 1 at 2.5 cm radius Layer 2 at 8 cm radius Pixel size18.4  m X 18.4  m Hit resolution10  m rms Position stability6  m (20  m envelope) Radiation thickness per layer X/X 0 = 0.37% Number of pixels436 M Integration time (affects pileup) 0.2 ms Radiation tolerance300 kRad Rapid detector replacement < 8 Hours critical and difficult more than a factor of 2 better than other vertex detectors (ATLAS, ALICE and PHENIX)

5. 5 Monolithic Active Pixel Sensors Standard commercial CMOS technology Only NMOS transistors inside the pixels Room temperature operation Sensor and signal processing are integrated in the same silicon wafer Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP signal is limited to <1000 electrons Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~10 pixels (20-30 μm pitch)‏ 100% fill-factor Fast readout Proven thinning to 50 micron MAPS pixel cross-section (not to scale)‏ Detector chips developed by Marc Winter’s group at IPHC in Strasbourg, France

6. 6 Sensor generation and RDO attributes Mimostar–2 30 µm pixel, 128 x 128 array 1.7 ms integration time 1 analog output Mimostar–3 30 µm pixel, 320 x 640 array 2.0 ms integration time 2 analog outputs Phase–1 30 µm pixel, 640 x 640 array 640 µs integration time, CDS 4 binary digital outputs Final (Ultimate) 18.4 µm pixel, 1024 x 1088 array ≤ 200 µs integration time, CDS, zero suppression 2 digital outputs (addresses) SensorSensor RDO 50 MHz readout clock JTAG interface, control infrastructure ADCs, FPGA CDS & cluster finding zero suppression ≤ 4 sensor simultaneous readout 160 MHz readout clock JTAG interface, control infrastructure zero suppression 120 sensor simultaneous readout 150 MHz readout clock JTAG interface, control infrastructure 400 sensor simultaneous readout (full system) DONE PROTOTYPED Gen 1 1 2 3

7. Silicon development Phase 1 –for use in the engineering run –on pixel CDS –on chip discriminators –binary hit read out –integration time 640  s Ultimate –for full installation run –functionality of Phase 1 plus zero suppression –integration time <200  s – suitable for full luminosity operation 7

8. 8 HFT PIXEL MAPS 120 GeV π - beam test at CERN Efficiency and Fake hit rate for Mimosa-16. 25um pixels at 20º C. This is the sensor design that is the basis for the HFT Phase-1 Pixel sensors. Efficiency and Fake hit rate for Mimosa-22. This sensor has the same design as the final HFT Pixel sensor. This sensor has been tested to 150k rad and maintained 99.5% efficiency with < 10 -4 fake hit rate. CMOS pixel sensor development: a fast readout architecture with integrated zero Suppression – C. Hu, PIXEL 2008 M.i.p. detection performances of a 100 μs read-out CMOS pixel sensor with digitised outputs – Marc Winter et. al., http://arxiv.org/PS_cache/arxiv/pdf/0902/0902.2717v1.pdf http://arxiv.org/PS_cache/arxiv/pdf/0902/0902.2717v1.pdf

9. Phase - 1 Extensively tested and characterized by the LBNL group –Multiple chips have been studied doing scans of operating parameters to determine optimum operation mode and determine permissible operation limits –Readout, firmware, testing tools mature, ready for probe testing of diced and thinned chips –so far ~100% yield of chips sampled from different locations on the wafer –Noise levels suitable for engineering run, but potential improvements have been identified and a second run is planned –near future – build a multi chip telescope and test in a minimum ionizing beam 9

10. 10 640 x 640 pixels, 30 um pitch, 160 MHz RDO clock, column level discriminators, 4 binary outputs, 640 us integration time Phase-1 – full reticle binary output prototype Phase-1 prototype sensors have been fabricated and tested at LBNL Phase-1 prototype on testing board.Initial observations of Phase-1 operation Digital output Analog output

11. Example parameter scan (Vref2) (one half of the chip seems to be sensitive to the parameter value) issue to be studied further at IPHC to understand cause Chip D1 (parameter scan) VREF2 = 810.887 V VREF2 = 820.898 V VREF2 = 830.909 V VREF2 = 840.920 V VREF2 = 850.931 V (@ICLPDISC = 80) Mean noise value Threshold dispersion Discriminator threshold voltage identified by 50% pixel hits (half below threshold half above threshold)

12. Ultimate status design is nearing completion will be submitted for first fabrication Feb 2010 12

13. 13 Readout studies: LVDS Data Path Testing Significant test of system data path at up to 200 MHz with 3 streams of pseudo-random data Xilinx Virtex-5 IODELAY element allows fine tuning of all individual input latching in 75 ps increments. Only system jitter affects data latching. Measured BER (bit error rate) of <10 -14 for 1 m 42 AWG and 6 m twisted pair data cables at 200 MHz and for 2.3 m 42 AWG at 160 MHz. The RDO system architecture is considered to be validated and we then worked on the design of the full functionality prototype system. 2 ns eye pattern opening for 1 m 42 AWG cables at 200 MHz Ladder mock-up with 1-to-4 LVDS fanout buffers Mass termination board + LU monitoring 42 AWG wires 24 AWG wires Virtex-5 based RDO system with RORC link to PC http://rnc.lbl.gov/hft/hardware/docs/LVDS/LVDS_test_report_1.pdf

14. current readout development work Preparing for probe test Develop multi chip readout capability (a modification of the current system) 14

15. HFT PIXEL mechanical development Stability analysis Thermal analysis Air flow vibration tests Thermal tests Fabrication development Installation mechanics 15

16. vertex projection from two points detector layer 1 detector layer 2 pointing resolution = (13  22GeV/p  c)  m from detector position error from coulomb scattering r2r2 r1r1 true vertex perceived vertex xx xx vv r2r2 r1r1 true vertex perceived vertex vv mm expectations for the HFT pixels first pixel layer more than 3 times better than anyone else 16

17. Mechanical Stability Movement from temperature changes Movement from humidity changes Deflection from gravity Movement induced by cooling air (to be addressed after thermal discussion) –how much air is required –vibration and static displacement Once the pixel positions are measured will they stay in the same place to within 20 µm? Issues that must be addressed: 17

18. Stability requirement drives design choices The detector ladders are thinned silicon, on a flex kapton/aluminum cable The large CTE difference between silicon and kapton is a potential source of thermal induced deformation even with modest 10-15 deg C temperature swings Two methods of control –ALICE style carbon composite sector support beam with large moment of inertia –Soft decoupling adhesive bonding ladder layers 18

19. Ladder design with soft adhesive (6 psi shear modulus) cable bundle drivers pixel chips adhesive wire bonds capacitors adhesive composite backer kapton flex cable adhesive: 3M 200MP 2 mil, film adhesive 19

20. FEA analysis of thermally induced deformation of sector beam FEA shell elements Shear force load from ladders 20 deg temperature rise Soft adhesive coupling 200 micron carbon composite beam end cap reinforcement Maximum deformation 9 microns (30 microns if no end cap) 20

21. FEA analysis - sector beam deformation – gravity load FEA shell analysis 120 micron wall thickness composite beam gravity load includes ladders maximum structure deformation 4 microns ladder deformation only 0.6 microns 21

22. Air cooling of silicon detectors - CFD analysis air flow path – flows along both inside and outside surface of the sector Silicon power: 100 raised to 170 mW/cm 2 (~ power of sunlight) 350 W total Si + drivers 22

23. Air cooling – CFD analysis air flow velocity 9-10 m/s maximum temperature rise above ambient: 12 deg C sector beam surface – important component to cooling dynamic pressure force 1.7 times gravity stream lines with velocity silicon surface temperature velocity contours 23

24. vibration modes with reinforced end cap The message –Lots of complicated modes close in frequency –End cap raises frequencies a bit 259 Hz 397 Hz 276 Hz 441 Hz 497 Hz 24

25. air velocity probe two positions shown capacitance vibration probe two positions shown carbon fiber sector beam wind tunnel setup to test vibration and displacement adjustable wall for air turn around air in air out C:\Documents and Settings\Howard Wieman\My Documents\aps project\mechanical\PXL phase 1 sept 2008\sector ph1 wind tunnel.SLDASM 25

26. Ladder vibration induced by cooling air system resolution limit all errors desired vibration target no reinforcement at the end 26

27. -167 µm 6 µm 17 µm -179 µm -248 µm measured static deformation from 9 m/s air flow -156 µm -163 µm -113 µm 9 µm 11 µm 1 µm open end reinforced end 27

28. measured vibration (RMS) induced by 9 m/s air flow 13 µm 14 µm 4 µm 6 µm 8 µm 3 µm 2 µm 11 µm 4 µm open end reinforced end 28

29. Full scale cooling tests Thermal camera window not shown > 300 CFPM air flow for verification of cooling capability 9 inch diameter tube mocks up MSC 29 dust collector for air supply

30. cooling test setup ladders with heaters mocking up expected heat loads –Flex pc with heater traces on most surfaces –One sector with ladders equipped with 50 micron silicon with platinum heater strip –ladders equipped with thermistor temperature sensors –thermal camera monitoring thinned silicon heaters 30

31. 12.2 m/s, ~300 W Thermistor temperature map for all the ladders on the inner and outer cylinders

32. 32 Thermal test results Hot spots for images at location 0-21 cm (3 cm step): 41.2, 42.5, 41.4, 41.6, 41.4, 40.5, 40.1, 38.3 ºC “sensor” heaters:~230 W Pt heaters:~25 W Driver heaters:~40 W Total:~295 W Airflow 12.2 m/s max min room ∆T above ambient room temperature: 11.5 deg C

33. Temperature in hot spots and averaged across approximately a die surface (location at 3 cm) Silicon temperature as a function of cooling air velocity

34. Thermal test conclusions Results reasonably consistent with CFD calculations Can handle the increased heat load of sensors with 30% increased air flow Need to recheck vibration with this 30% increase in air velocity 34

35. Ladder and sector manufacturing Tooling has been developed and tested for efficient fabrication of ladders and bonding of ladders to sectors Sector production demonstrated, will possibly work on improved shape control 35

36. Sector structures 36

37. ladder fabrication and tooling 37

38. ladder fabrication and tooling 38

39. ladder fabrication and tooling 39 finalizing mechanical designs and developing rapid production methods

40. ladder fabrication and tooling 40 ladder with silicon heater chips (50  m thick)

41. wire bonding 50  m silicon to flex PC 41 vacuum chuck to secure flex and silicon flat against solid surface to remove bounce Any bounce then no bond Good News after a couple of minor modifications to the vacuum chuck the wire bonding machine is happy Rhonda is happy

42. ladder to sector tooling fixtures (4 stations) 42

43. Designs for installation of PXL a well controlled method for installation of the pixel detector is being developed with emphasis on ease of operation and avoidance of detector risk The PXL assembly will be enclosed in a carrying box that is equipped for transfer of the detector assembly into the PXL support tube The operation should work with and without the pole tip installed 43

44. PXL installation PXL supported in carrying box on rails assembly designed to position around beam pipe and supports box can moved into the MSC such that rails in the box couple to the support rails in the MSC 44

45. 45 box positioning video

46. box alignment and PXL transfer box positioned to align rails, but rails have a slightly flexible joint so that less than perfect alignment is required to move box forward to engage taper pins 46 with rails connected, slide PXL until carriage is engaged on the MSC rails

47. final installation steps 47 remove box rails slide detector home remove box and connect services