1. University of Tehran 1 Interface Design Compute Memory Timing Omid Fatemi (omid@fatemi.net)

2. University of Tehran 2 Outline Connecting to micro-processor Timing of microprocessor Timing of memory Interfacing memory

3. University of Tehran 3 Typical Interface Design Connect ComputeConveyCooperate Sense Reality Touch Reality Connect Transform Embedded Systems Micros Assembler, C Real-Time Memory Peripherals Timers DMA PC interfaces HCI Busses Protocols Standards PCI IEEE488 SCSI USB & FireWire CAN

4. University of Tehran 4 Processor Timing Diagram for any memory read machine cycle

5. University of Tehran 5 Processor Timing Diagram for any memory write machine cycle

6. University of Tehran 6 When interfacing memory chips to a microprocessor, consider the following: TAVDV – address access time TRLDV – read access time TDVWH – memory setup time TWHDX – data hold time TWLWH – write pulse width Refer to 8088 data manual8088 data manual

7. University of Tehran 7 Address Access Time (TAVDV)

8. University of Tehran 8 Timing Requirements during Memory Read TAVDV –3TCLCL – TCLAV – TDVCL –Address Access Time –from Address is Valid to Data is Valid

9. University of Tehran 9 Read Access Time (TRLDV)

10. University of Tehran 10 Timing Requirements during Memory Read TRLDV –2TCLCL – TCLRL – TDVCL –Read Access Time –from Read Signal is Low to Data is Valid

11. University of Tehran 11 Memory Setup Time (TDVWH)

12. University of Tehran 12 Timing Requirements during Memory Write TDVWH –2TCLCL – TCLDV +TCVCTX –Memory Setup Time –from Data is Valid to Write Signal is High

13. University of Tehran 13 Data Hold Time (TWHDX)

14. University of Tehran 14 Timing Requirements during Memory Write TWHDX –TCLCH – X –Data Hold Time (after WR ’ ) –from Write Signal is High to Data is Invalid (Inactive)

15. University of Tehran 15 Write Pulse Width / Write- Time (TWLWH)

16. University of Tehran 16 Timing Requirements during Memory Write TWLWH –2TCLCL – Y –Write Pulse Width / Write-Time –from Write Signal is Low to Write Signal is High

17. University of Tehran 17 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

18. University of Tehran 18 Computation of Timing Requirements for 8088 using a 4Mhz Clock TAVDV  3TCLCL – TCLAV max – TDVCL min  3(250 ns) – 110 ns – 30 ns  610 ns TRLDV  2TCLCL – TCLRL max – TDVCL min  3(250 ns) – 165 ns – 30 ns  555 ns

19. University of Tehran 19 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

20. University of Tehran 20 Computation of Timing Requirements for 8088 using a 4Mhz Clock TDVWH  2TCLCL – TCLDV max +TCVCTX min  2(250 ns) – 110 ns + 10 ns  400 ns TWHDX  TCLCH – X  118 ns – 30 ns  88 ns TWLWH  2TCLCL – Y  2(250 ns) – 60 ns  440 ns

21. University of Tehran 21 Timing Requirements for 8088 using a 4Mhz Clock TAVDV = 610 ns TRLDV = 555 ns TDVWH = 400 ns TWHDX = 88 ns TWLWH = 440 ns

22. University of Tehran 22 Can we interface a 6264 to the 8088 chip which uses a 4MHz clock?

23. University of Tehran 23 Timing Requirements for 6264 SRAM TAVDV = ? TRLDV = ? TDVWH = ? TWHDX = ? TWLWH = ?

24. University of Tehran 24 HM6264B Series Read TIMING REQUIREMENTS HZ2 Chip deselection in to output in high-Z (CS2’) 0 30 0 35 ns t OHZ Output disable to output in high-Z 0 30 0 35 ns t OH Output hold from address change 10 ns

25. University of Tehran 25 HM6264B Series Write TIMING REQUIREMENTS

26. University of Tehran 26 HM6264B Series Read Timing Diagram

27. University of Tehran 27 HM6264B Series Write Timing Diagram

28. University of Tehran 28 Timing Requirements for 6264 SRAM TAVDV = t AA TRLDV = t OE TDVWH = t DW TWHDX = t DH TWLWH = t WP

29. University of Tehran 29 Timing Requirements for HM6264B-8L TAVDV = t AA = ? TRLDV = t OE = ? TDVWH = t DW = ? TWHDX = t DH = ? TWLWH = t WP = ?

30. University of Tehran 30 HM6264B Series Read TIMING REQUIREMENTS

31. University of Tehran 31 HM6264B Series Write TIMING REQUIREMENTS

32. University of Tehran 32 Timing Requirements for HM6264B-8L TAVDV = t AA = 85 ns TRLDV = t OE = 45 ns TDVWH = t DW = 40 ns TWHDX = t DH = 0 ns TWLWH = t WP = 55 ns

33. University of Tehran 33 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L

34. University of Tehran 34 Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?

35. University of Tehran 35 Timing Requirements for 2764 EPROM TAVDV = ? TRLDV = ? TDVWH = ? TWHDX = ? TWLWH = ?

36. University of Tehran 36 M2764A Read Mode AC Characteristics

37. University of Tehran 37 M2764A Read Mode Timing Diagram

38. University of Tehran 38 Timing Requirements for 2764 EPROM TAVDV = t AVQV TRLDV = t GLQV TDVWH = N/A TWHDX = N/A TWLWH = N/A

39. University of Tehran 39 Timing Requirements for 2764 EPROM TAVDV = t AVQV = ? TRLDV = t GLQV = ? TDVWH = N/A TWHDX = N/A TWLWH = N/A

40. University of Tehran 40 M2764A Read Mode AC Characteristics

41. University of Tehran 41 Timing Requirements for M2764A-3 TAVDV = t AVQV = 180 ns TRLDV = t GLQV = 65 ns TDVWH = N/A TWHDX = N/A TWLWH = N/A

42. University of Tehran 42 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3

43. University of Tehran 43 What if we need to interface a “slow” memory to the 8088?

44. University of Tehran 44 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain “slow” memory chip

45. University of Tehran 45

46. University of Tehran 46 Recall:Write Pulse Width / Write-Time (TWLWH)

47. University of Tehran 47 Write Pulse Width / Write-Time (TWLWH) w/ 1 wait state

48. University of Tehran 48 Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain memory chip caused by 1 wait state during a memory write on the “slow” memory chip

49. University of Tehran 49 How do we produce a wait state? By turning the READY input of the 8088 microprocessor to LOW

50. University of Tehran 50

51. University of Tehran 51 Requirements for the READY input of the 8088

52. University of Tehran 52 Requirements for the RDY of the 8284

53. University of Tehran 53

54. University of Tehran 54