1. RISC, CISC & MIPS Bryan Duggan

2. What is this lecture about? Different architectures RISC CISC MIPS Registers Memory SPIM

3. What is “Computer Architecture” Computer Architecture = Instruction Set Architecture + Machine Organization

4. Example Architectures Digital Alpha(v1, v3)1992-97 HP PA-RISC(v1.1, v2.0)1986-96 Sun Sparc(v8, v9)1987-95 SGI MIPS(MIPS I, II, III, IV, V)1986-96 Intel(8086,80286,80386,1978-96 80486,Pentium, MMX,...)

5. Forces on Computer Architecture Computer Architecture Technology Programming Languages Operating Systems History Applications (A = F / M) Constraints e.g. cost, energy

6. Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language BasedConcept of a Family (B5000 1963)(IBM 360 1964) General Purpose Register Machines Complex Instruction SetsLoad/Store Architecture RISC (Vax, Intel 432 1977-80) (CDC 6600, Cray 1 1963-76) (Mips,Sparc,HP-PA,IBM RS6000,...1987)

7. Processor Performance (SPEC) RISC introduction Did RISC win the technology battle and lose the market war? performance now improves ­ 50% per year (2x every 1.5 years)

8. RISC/CISC Complex Instruction Set Computer  Intel x86  DEC VAX, PDP11  Motorola 68k  IBM 360, 370 Complex instructions bring the hardware closer to high-level languages Memory was expensive  Fewer, more powerful instructions á Smaller programs á More space for data

9. CISC - ISA Instruction Set Architecture Addressing Modes Additional Instructions Procedure and function call  Procedure call overhead is significant Registers (state of the processor) must be saved and restored Mot 68k MOVEM x86 PUSH, POP Array Indexing  y = x[i][j][k] VAX Math functions  sqrt, sin, log,...Intel x86 + 8087 Motorola 68k? Yet more instructions! Graphics support  MMX

10. CISC - ISA Instruction count Usually almost 256  Maximum number of 8-bit opcodes! Powerful instructions Many microcode steps  Multiple cycle latency  Faster in microcode than user’s program Added some complexity to interrupt handling, page faulting, etc Instructions too long to be uninterruptible! Variable length, multiple formats  1 to 17 bytes

11. CISC - ISA critique Studies of compilers showed Many instructions unused  DEC even dropped an indexed memory access, post-decrement y = x[i--] from the ISA going from PDP -> VAX Compiler writers were sometimes simply not using complex instructions when they were appropriate  because they could write faster sequences of simple instructions for the most common cases Operand Constants  -15 to + 15 56%  -511 to + 511 98% 12 Words of storage for sub routines 95%

12. CISC Irrespective of its performance... Complex hardware is expensive Speed improvements Irregular (long design times) Long lead times to market  Instruction set & chip hardware become more complex with each generation of computers.  Number of control words and number of clock cycles vary between instructions. Difficult to implement instruction pipelining.

13. 80x86 1978: The Intel 8086 is announced (16 bit architecture) 1980: The 8087 floating point coprocessor is added 1982: The 80286 increases address space to 24 bits, +instructions 1985: The 80386 extends to 32 bits, new addressing modes 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance) 1997: MMX is added “This history illustrates the impact of the “golden handcuffs” of compatibility

14. RISC Characteristics No universally accepted definition Most of the following Instructions are conceptually simple Instructions are of a uniform length Instructions use one (or very few) instruction formats Instruction set is “orthogonal”  Little overlapping of instruction functionality Instructions use very few addressing modes Architecture is a load-and-store architecture  Only LOAD and STORE instructions reference memory  All operate instructions are register-to-register The ISA supports few data types

15. RISC Characteristics, (Cont'd). Other possible attributes Almost all instructions execute in one clock cycle  Implementation detail Architecture takes advantage of strengths of software  All reasonable architectures do Architecture should have many registers  Not part of RISC  Useful, however, for speeding up CPU

16. Reduced Instruction Set Computer No memory-memory instructions Data loaded to registers lw $3, 0($2) Data stored from registers st $4,40($5) Arithmetic, logical, etc operations are all  Register -> Register  Mostly 3-operand type: op dest_reg, src_regA, src_regB  Mostly 1-cycle in ALU á Throughput: 1 instruction/cycle á Register Windows

17. RISC Simplicity of RISC instructions permits high clock rates long-latency ALU instructions are divided further as necessary  MIPS R4000 : 8-stage pipeline All instructions 32-bits Simplifies fetch

18. RISC - Simple Hardware, Complex Compiler Basic hardware is simple and hard-wired  ie no microcode but … - Pipeline stalls can reduce throughput Optimising Compiler needed Fully exploit capabilities  Dependence Analysis ç Instruction re-ordering ç Avoid pipeline stalls

19. RISC Disadvantages  A more sophisticated compiler is required.  A sequence of RISC instructions is needed to implement complex instructions.  Require very fast memory systems to feed them instructions.  Performance of a RISC application depend critically on the quality of the code generated by the compiler.

20. MIPS In 1981 John Hennessy designed a different RISC chip which he called MIPS (Microprocessor without Interlocking Pipeline Stages). MIPS processors are quite powerful. Used in high performance embedded systems. An embedded computer is a computer incorporated into another device such as a car. Used in workstations to produce the special effects in many Hollywood movies (including the new version of Star Wars, Jurassic Park and Toy Story) Also used in Nintendo 64 game machines. It is estimated that more MIPS are sold that Intel microprocessors.

21. Memory Organisation Memory consists of a number of cells. Each holds one eight bit number or byte Memory cells are numbered starting at zero up to the maximum allowable amount of memory

22. MIPS Memory Organisation

23. MIPS Registers Processor’s memory consists of a number of registers Each register has a certain function The most important is the Program Counter (PC). It points to the memory address of the next instruction to be executed Contains 32 General Purpose Registers, numbered 0- 31 Register n designated by $n or Rn There is also 16 floating point registers $f0.. £f15 to hold numbers in floating point form such as 3.459 x 10

24. MIPS Registers

25. SPIM SPIM is a simulator that runs programs for the MIPS R2000/R3000 RISC computers SPIM can read and immediately execute files containing assembly language. Why use a simulator ? Not manyMIPS workstations around Easier to write assembly language as current computers more difficult to understand Detect more errors Another approach is to use specially designed circuit boards with processor, memory and input/output devices. However the edit – assemble – load development cycle is slower and such systems are prone to hardware problems

26. I/O Organisation SPIM uses an operating system or Kernel to do I/O To do this, it makes a system call Kernel implements these calls by talking directly to the hardware SPIM provides a small set of 10 operating system like services through the system call (syscall) instruction To request a service, a program loads the system call code into register $v0 and arguments into registers $a0..$a3 System calls that return values put their result in register $v0

27. SPIM System Calls

28. Summary RISC machines are based on the idea that by speeding up the commonest simple instructions one could afford to pay a penalty in the unusual case of more complex operations and make a large gain in performance Memory consists of a number of cells, each holds one eight-bit number or byte A programs address space consists of three parts, the text, data and stack segment The MIPS processor contains 32 general purpose registers An application program asks the kernel to do I/O by making system calls SPIM is a simulator that runs programs for the MIPS computers