1. ENG241 Digital Design Week #6 Sequential Circuits (Part A)

2. 2 Week #6 Topics  Sequential Circuit Definitions  Latches  Flip-Flops  Delays in Sequential Circuits  Clock Gating

3. 3Resources  Chapter #6, Mano Sections 6.1 Sequential Circuit Definition 6.2 Latches 6.3 Flip-Flops

4. 4 Combinational/Sequential Circuits  Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer.  Combinational circuits cannot remember what happened in the past (i.e. outputs are a function of current inputs).  In certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past.  Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits.

5. 5 Remembering States

6. 6 Sequential Circuits  Information that is stored in the storage elements represent the state of the system.  The outputs will depend on the inputs and present state of the storage elements. Storage Elements

7. 7 Types of Sequential Circuits  Two main types and their classification depends on the times at which their inputs are observed and their internal state changes.  Synchronous  State changes synchronized by one or more clocks  Asynchronous  Changes occur independently

8. 8 Signal Examples Over Time Analog Asynchronous Synchronous Time Continuous in value & time Discrete in value & continuous in time Discrete in value & time Digital

9. 9 Clocking of Synchronous Circuits  Changes enabled by clock

10. 10Comparison  Synchronous  Easier to analyze because can factor out gate delays  Speed of the system is determined by the clock (maybe slowed!)  Asynchronous  Potentially faster  Harder to analyze We will look mostly at synchronous

11. 11 Basic Storage (How?) 1. Apply low or high for longer than t pd But we are interested in storing information indefinitely! 2. Feedback will hold value However we want inputs to our circuitry!

12. 12Latches  Are storage elements that can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states.  Latches are asynchronous circuits  Latches are used to build more complex synchronous circuits such as Flip Flops.

13. 13 SR (set-reset) Latches:  Replace the inverters with NAND, NOR Gates  Basic storage made from gates  The information can be changed  S & R both 0 in “resting” state  Have to keep both from 1 at same time

14. 14Operation Reset, Q=0 Keep State Set, Q=1Undefined!

15. 15 Latch  Similar – made from NANDs S & R both 1 in “resting” state Have to keep both from 0 at same time

16. 16 Add Control Input: SR Latch  An additional input determines when the state of the latch can be changed!  Can we avoid the undefined state?

17. 17 D-type Latch No illegal state

18. 18 Transparency of Latches  The state of a latch is allowed to switch by a momentary change in value on the control input.  As long as C (the trigger ) is high, state can change! transparency  This is called transparency What is wrong with transparency?

19. 19 Effects of Transparency  Output of one latch may feedback As soon as the input changes, shortly thereafter the corresponding output changes to match it. The final state will depend on how long the clock pulse stays at level logic 1! (unreliable) We need to predict the outputs at a certain moment in time! o Want to change latch state once Depending on inputs at time of clock Storage Element Clock

20. 20Flip-Flops  Ensure only one transition  Two major types 1. Master-Slave (level triggered)  Two stage  Output not changed until clock disabled 2. Edge triggered  Change happens when clock level changes

21. 21 Master-Slave SR Flip-Flop  When Master is enabled, Slave is disabled!  Output Q will not change when inputs change SCRSCR SCRSCR SCRSCR SR Latch Master Slave

22. 22 Timing Diagram  Trace the behavior  Note the illegal state  Is it transparent? 1 0 0 1

23. 23 Have We Fixed the Problem?  Output no longer transparent Combinational circuit can use last values New inputs appear at latches Not sent to output until clock low In one clock cycle we can predict what will happen  Note: Master-Slave = pulse triggered

24. 24 JK Flip Flop  The JK Flip Flop is a modified version of the SR Flip Flop which eliminates the undesirable condition that leads to undefined outputs.  The JK flip flop performs three operations: 1. Set Q to 1 2. reset Q to 0 3. complement the output

25. 25 Master-Slave JK Flip Flop The J input sets the flip flop to 1. The K input resets the flip flop to 0. When both J and K are enabled, the output is complemented.

26. 26 Edge-Triggered Flip-Flops  An Edge Triggered Flip-Flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal.  New state latched on clock transition  Low-to-high or high-to-low  Changes when clock high are ignored

27. 27 Clock Responses We can classify Flip/Flops according to the response to the clock.

28. 28 Edge Triggered D-Flip-Flop DCDC SCRSCR

29. 29 Characteristic Tables  Define the logical properties of a flip flop by describing its operations in tabular form.  They define the next state as a function of the inputs and the present state.  Q(t) refers to the present state prior to the application of a clock edge.  Q(t + 1) refers to the next state one clock period later.  Clock edges are not listed as inputs but are implied by the transition from t to t + 1.

30. 30 D FF Characteristic Table The Characteristic Equation: Q(t + 1) = D(t)

31. 31 Edge-Triggered D Flip Flop: Graphic Symbols  The triangle is called: dynamic indicator

32. 32 Other Flip Flops  Other types of flip flops can be constructed by using the D flip flop and external logic. The two most commonly used are: 1. Edge triggered JK flip flops 2. T flip flops

33. 33 JK Characteristic Table Characteristic Equation: Q(t+1) = J(t) Q’(t) + K’(t)Q(t)  Utilize the equation to create a JK flipflop from an existing D flipflop

34. 34 Edge-Triggered JK Flip Flop Q(t+1) = J(t) Q’(t) + K’(t)Q(t)

35. 35 Analysis of the JK Circuit  The circuit applied to the D input is D = JQ’ + K’Q I. If J = 1 and K = 0, D = Q + Q’ = 1 (Set) II. If J = 0 and K = 1, D = 0 (Reset) III. If J = K = 0, D = Q, (No Change) IV. If J = K = 1, D = Q’ (Complement)

36. 36 T Flip Flop T  The T Flip Flop is a complementing flip flop.  How can we obtain a T Flip Flop from a JK Flip Flop or D Flip Flop? Q(t+1) = TQ’(t) + T’Q(t)

37. 37 T Flip Flop  The T flip flop can be obtained from a JK flip flop when inputs J and K are tied together.

38. 38 Characteristic Equations  The D flip flop can be expressed as:  Q(t + 1) = D  The JK flip flop can be expressed as:  Q(t + 1) = JQ’ + K’Q  The T flip flop can be expressed as:  Q(t + 1) = TQ’ + T’Q  Characteristic Tables are used to 1. Derive the characteristic equations, 2. Analyze Sequential Circuits.

39. 39 JK- Characteristic Equation Q(t+1) = J(t) Q’(t) + K’(t)Q(t) 000^0 001^1 010^0 011^0 100^1 101^1 110^1 111^0 JKQCLKQ+ 0011 1001 Q JK 0 1 00 01 11 10

40. 40 Standard Symbols – Latches  Circle at input indicates negation

41. 41 Symbols – Master-Slave  Inverted L indicates postponed output  Circle indicates whether enable is positive or negative

42. 42 Symbols – Edge-Triggered  Arrow indicates edge trigger

43. 43 Direct Inputs  Set/Reset independent of clock Direct set or preset Direct reset or clear  Often used for power-up reset

44. 44 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral (algorithmic) Registers State machines Test benches Sequential statements

45. 45 VHDL For Sequential Circuits  Several techniques have been discussed in class to describe the architecture of combinational logic circuits: 1. Data Flow 2. Structural  Statements used in “Data Flow” and “Structural” descriptions can be executed in parallel i.e. concurrently.  Another technique to describe the architecture of any circuit is to use Behavioral description.  The process statement is usually used to describe sequential designs.  The process statement consists of only sequential statements

46. 46 VHDL For Sequential Circuits  To describe sequential circuits we usually use the “process” statement.  A process statement consists of 1. Sensitivity list  Process (CLK, RESET) This list enumerates exactly which signals causes the process statement to be executed. (Only events on these signals cause the process statement to be executed!) 2. Declarative region  Process (CLK, RESET) …… (declare local vars) Begin ….. END

47. 47 VHDL for Positive Edge Triggered D-FF -- positive Edge-Triggered D flip-flop with reset -- VHDL Process Description library ieee; use ieee.std_logic_1164.all; entity dff is port (CLK, RESET, D : in std_logic; Q : out std_logic); end dff; architecture pet_pr of dff is begin process (CLK, RESET) begin if (RESET = `1’) then Q <= `0’; elsif (CLK’event and CLK = `1’) then - - you can use rising_edge(CLK) instead! Q <= D; end if; end process; end;

48. 48 Flip-Flop Timing Setup time (t s )– time that D must be available before clock edge Hold time (t h )– time that D must be stable after clock edge

49. 49Summary  Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer.  Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits.  Latches are storage elements that are asynchronous, transparent and are used to build more complex synchronous circuits such as Flip- Flops.  Flip-flops avoid the transparency problem faced by latches and are either Master-Slave pulse active or edge triggered.  Characteristic tables will be used to analyze the behavior of sequential circuits.

50. 50

51. 51 Propagation Delay  Propagation delay – time after edge when output is available

52. 52 Positive D-Type Edge Triggered DCDC SCRSCR

53. 53 Have We Fixed the Problem?  Output no longer transparent Combinational circuit can use last values New inputs appear at latches Not sent to output until clock low In one clock cycle we can predict what will happen  But changes at input of FF when clock high trigger next state Transient state where S goes high caused by gate delays As clock faster, more problems Have to guarantee circuit settles while clock low  Note: Master-Slave = pulse triggered

54. 54 Clock Pulse Requirements  Basically a max clock frequency

55. 55 Clock Gating  Can gate clocks (to keep any FF from changing states, for example)  Clock gating used to reduce power drain  However, can cause clock skew  Clock edges at different times on different FFs  Clock skew also caused by wire lengths over chip

56. 56 T Flip Flop  The T flip flop can also be obtained from a D flip flop by using an XOR as the input for D.

57. 57 Master-Slave JK Flip Flop Q(t+1) = J(t) Q’(t) + K’(t)Q(t)