1. EE/CS 481 Spring 2008 1Founder’s Day, 2008 University of Portland School of Engineering Project Golden Eagle CMOS Fast Fourier Transform Processor Team Sandra Pellecer Neil Tuttle Ziyuan Zhang Advisor Dr. Aziz Inan, Dr. Peter Osterberg Industry Representative Mr. David Dunning Intel

2. EE/CS 481 Spring 2008 2Founder’s Day, 2008 University of Portland School of Engineering Agenda Introduction Sandra Pellecer Background Sandra Pellecer Methods Ziyuan Zhang Results Neil Tuttle Conclusions Sandra Pellecer Demonstration Team

3. EE/CS 481 Spring 2008 3Founder’s Day, 2008 University of Portland School of Engineering The Fast Fourier Transform (FFT) Efficient algorithm used to compute the Discrete Fourier Transform Used in digital signal processing Used to analyze, filter, and generate digital signals http://www.evia.net/greekamp/granalyzer.gif

4. EE/CS 481 Spring 2008 4Founder’s Day, 2008 University of Portland School of Engineering Time Domain Vs. Frequency Domain (MATLAB) Dr. Hoffbeck : fsdemo.m

5. EE/CS 481 Spring 2008 5Founder’s Day, 2008 University of Portland School of Engineering 1Hz sine + 3Hz sine Dr. Hoffbeck : fsdemo.m

6. EE/CS 481 Spring 2008 6Founder’s Day, 2008 University of Portland School of Engineering 1Hz sine + 3Hz sine + 5Hz sine Dr. Hoffbeck : fsdemo.m

7. EE/CS 481 Spring 2008 7Founder’s Day, 2008 University of Portland School of Engineering Many sine waves Dr. Hoffbeck : fsdemo.m

8. EE/CS 481 Spring 2008 8Founder’s Day, 2008 University of Portland School of Engineering Advantages of the FFT The FFT is faster than the DFT DFT FFT

9. EE/CS 481 Spring 2008 9Founder’s Day, 2008 University of Portland School of Engineering Project Description Design CMOS MOSIS chip set to compute Fast Fourier Transform Initial Plan (Summer ’07) –Input signal: 4 samples, 4-bit precision –Output signal: 4 samples, 8-bit precision Final Plan (Fall ’07) –Input signal: 8 samples, 4-bit precision –Output signal: 8 samples, 9-bit precision

10. EE/CS 481 Spring 2008 10Founder’s Day, 2008 University of Portland School of Engineering MOSIS Educational Program (MEP) Nationwide educational grant program Sponsors schools such as Stanford, MIT, and Berkeley to design and manufacture integrated circuits $4,000 grant for this project

11. EE/CS 481 Spring 2008 11Founder’s Day, 2008 University of Portland School of Engineering Implementation Challenges FFT requires complex (real and imaginary) numerical computations FFT requires a large number of addition and multiplication operations

12. EE/CS 481 Spring 2008 12Founder’s Day, 2008 University of Portland School of Engineering Summer ‘07 Studied FFT Algorithm Completed FFT dataflow diagram Created B2Logic components (adder, multipliers) Connect components and test Completed 4 sample, 4-bit FFT circuit

13. EE/CS 481 Spring 2008 13Founder’s Day, 2008 University of Portland School of Engineering Fall ‘07 Completed 8 sample, 4-bit FFT circuit Tested and debugged circuit –Circuit output vs. MATLAB & custom simulation program Completed MOSIS CMOS chip set design by Thanksgiving

14. EE/CS 481 Spring 2008 14Founder’s Day, 2008 University of Portland School of Engineering Design Tools B2Logic –Digital schematic capture and simulation B2Logic to ABEL Translator (BAT) –Converts B2Logic files to ABEL for CPLD prototyping B2Logic to L-Edit Translator (BLT) –Automatically creates netlist for CMOS IC

15. EE/CS 481 Spring 2008 15Founder’s Day, 2008 University of Portland School of Engineering Design Tools (cont.) L-Edit –Automatically generates chip set layout from netlist MATLAB

16. EE/CS 481 Spring 2008 16Founder’s Day, 2008 University of Portland School of Engineering B2Logic Problems Circuit was too large for B2Logic Split design into two parts

17. EE/CS 481 Spring 2008 17Founder’s Day, 2008 University of Portland School of Engineering MOSIS FFT Chip Set Block Diagram

18. EE/CS 481 Spring 2008 18Founder’s Day, 2008 University of Portland School of Engineering Chip 1 Schematic Diagram

19. EE/CS 481 Spring 2008 19Founder’s Day, 2008 University of Portland School of Engineering Chip 1 L-EDIT Layout

20. EE/CS 481 Spring 2008 20Founder’s Day, 2008 University of Portland School of Engineering Chip 1 L-EDIT Layout

21. EE/CS 481 Spring 2008 21Founder’s Day, 2008 University of Portland School of Engineering Chip 1 Pinout

22. EE/CS 481 Spring 2008 22Founder’s Day, 2008 University of Portland School of Engineering Chip 2 Schematic Diagram

23. EE/CS 481 Spring 2008 23Founder’s Day, 2008 University of Portland School of Engineering Chip 2 L-EDIT Layout

24. EE/CS 481 Spring 2008 24Founder’s Day, 2008 University of Portland School of Engineering Chip 2 Pinout

25. EE/CS 481 Spring 2008 25Founder’s Day, 2008 University of Portland School of Engineering Technical Details 5V, 1.5 micron process AMI Semiconductor Both IC dies are 5mm x 5mm Both ICs contain about 2,000 logic gates Both ICs contain about 20,000 MOSFETs (transistors)

26. EE/CS 481 Spring 2008 26Founder’s Day, 2008 University of Portland School of Engineering Project Block Diagram

27. EE/CS 481 Spring 2008 27Founder’s Day, 2008 University of Portland School of Engineering Project Schematic

28. EE/CS 481 Spring 2008 28Founder’s Day, 2008 University of Portland School of Engineering

29. EE/CS 481 Spring 2008 29Founder’s Day, 2008 University of Portland School of Engineering

30. EE/CS 481 Spring 2008 30Founder’s Day, 2008 University of Portland School of Engineering MOSIS CMOS Chips MOSIS CMOS Chips

31. EE/CS 481 Spring 2008 31Founder’s Day, 2008 University of Portland School of Engineering Conclusions FFT is an efficient algorithm for computing the Discrete Fourier Transform MOSIS CMOS chip set is intended to improve the speed of digital signal processing algorithms First time the FFT has been successfully achieved as a senior design project

32. EE/CS 481 Spring 2008 32Founder’s Day, 2008 University of Portland School of Engineering Future Enhancements Combine into single IC Improve precision Implement pipelining Implement inverse FFT

33. EE/CS 481 Spring 2008 33Founder’s Day, 2008 University of Portland School of Engineering Demo Block Diagram

34. EE/CS 481 Spring 2008 34Founder’s Day, 2008 University of Portland School of Engineering Infinite Sample FFT (MATLAB)

35. EE/CS 481 Spring 2008 35Founder’s Day, 2008 University of Portland School of Engineering 512 Sample FFT (MATLAB)

36. EE/CS 481 Spring 2008 36Founder’s Day, 2008 University of Portland School of Engineering 128 Sample FFT (MATLAB)

37. EE/CS 481 Spring 2008 37Founder’s Day, 2008 University of Portland School of Engineering 32 Sample FFT (MATLAB)

38. EE/CS 481 Spring 2008 38Founder’s Day, 2008 University of Portland School of Engineering 16 Sample FFT (MATLAB)

39. EE/CS 481 Spring 2008 39Founder’s Day, 2008 University of Portland School of Engineering 8 Sample FFT (MATLAB)

40. EE/CS 481 Spring 2008 40Founder’s Day, 2008 University of Portland School of Engineering 4 Sample FFT (MATLAB)

41. EE/CS 481 Spring 2008 41Founder’s Day, 2008 University of Portland School of Engineering Demonstration (8 Sample FFT) Input: 3.6kHz

42. EE/CS 481 Spring 2008 42Founder’s Day, 2008 University of Portland School of Engineering Acknowledgements Mr. Dave Dunning Dr. Joseph Hoffbeck Dr. Aziz Inan Dr. Wayne Lu Dr. Peter Osterberg Sandy Russell Dr. Karen Ward Mosis Educational Program (MEP) Thank You.

43. EE/CS 481 Spring 2008 43Founder’s Day, 2008 University of Portland School of Engineering

44. EE/CS 481 Spring 2008 44Founder’s Day, 2008 University of Portland School of Engineering FFT dataflow