1. Lecture 18: Dynamic Reconfiguration II November 12, 2004 ECE 697F Reconfigurable Computing Lecture 18 Dynamic Reconfiguration II

2. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Overview How an FPGA is configured is an important issue. Many techniques /possibilities. Existing approaches have serious limitations. Need to compress bit streams to allow for rapid reconfiguration First approach: wild card -> write multiple configurable cells at the same time. Second approach: run length encoding -> attempt to take advantage of regularity in configuration stream.

3. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Compression Techniques Effectively we can consider an FPGA device as a collection of cells, each with (x, y) location. Instead of using a serial bit stream, could consider loading data cell-by- cell like a standard memory. Specify location of cell through use of two registers. Row R1R1 R0R0 Col C1C1 C0C0 00011011 00 01 10 11 Logic Cluster

4. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Wild Card Registers In many FPGA devices created recently it is possible to write multiple cells at the same time. X in “wild card position” indicates multiple writes to a row/col Key is to minimize total writes to allow for data compression. What does this look like. 00011011 00 01 10 11 Row Col row R1R1 R0R0 00 col C1C1 C0C0 00 wc row 00 wc col 00

5. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Dealing with Don’t Touches Some locations shouldn’t be overwritten at all due to previous constraints. Others can be written with one value and then overwritten with another 00011011 00 01 10 11 Row Col 2 DT 2 2 3 1 1 1 1 1 3 3 3 2 All eight can be covered with just one write 00011011 00 01 10 11 Row Col row R1R1 R0R0 00 col C1C1 C0C0 00 wc row XX wc col 0X 1 1 1 1 1 X X X

6. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Parallels to Logic Minimization Zeros used to represent Don’t Touch cases. Every time I solve for a specific configuration more Don’t Touches will be created. Ordering of writes will have an impact on the number of Don’t Cares under consideration. Maximizing Don’t Cares a positive step. 00011011 00 01 10 11 0 0 0 0 0 0 1 1 1 1 1 X X X 0 0

7. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Modeling the Problem as Logic Optimization °Order configuration groups by frequency of occurrence. °Rather than truth table, represent grid locations as “cubes” both for on-set and don’t care set. °Logic optimization packages like Espresso effective in minimizing “cubes” °Note cubes that cover most locations ° 1000 1 00-- 1 0001 1 ----  -000 1 0010 1 0011 1 0000 -

8. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Wild Card Minimization Sequence Read in file and group all addresses with same value. Sort groups in decreasing order of number of addresses to be written Pick first group and label addresses as on-set including unoccupied locations Run logic minimization (Espresso) on group. Pick Espresso cube that covers most unoccupied addresses Reinsert other addresses back in queue Iterate

9. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Minimization Ordering Clearly selecting configuration 6 first is advantageous 3 writes needed to cover this configuration. Some values never benefit from Don’t Cares due to presence of Don’t Touches 3 cycles needed for each write. Might be possible to show additional optimization? 00011011 00 01 10 11 6 6 6 6 6 5 6 6 66 6 6 6 6 5 6

10. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Wild Card Minimization Results Sizable reduction in overall writes needed – only 17% of original needed Implications for power? If only a portion of the design changed not clear of benefit.

11. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Alternate Approach Rather than using wild card register, instead consider encoding information. Compress information at the source (e.g. local workstation), decompress using hardware embedded in the device. Takes advantage of sequences of information that are regular. Independent of decode hardware inside the FPGA (e.g. row, column, wild card registers).

12. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Run-length Compression * Send a sequence of values as a collection of three pieces of data 100, 103, 106, 109, 112 Base = 100 offset = 3 length = 4 Primarily useful for addresses but may be applicable to data as well. Constrained by data sizes for the three values.

13. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Lempel-Ziv Compression Run-length encoding deals with repetition of a single value Lempel-Ziv deals with repetition of a number of values up to some window size. example CBADAFAL if next three pieces are: A, B, M We can use a codeword: pointer = 3 length = 2 last symbol = M Also CBADAFAL next 13 pieces of data BCBCBCBCBCBCD pointer=2 length=12

14. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Ordering of Values Clearly some sequences are better aligned than others: -ABCDABCBAC This reordering can be made adaptive based on “tuning” parameters derived from a number of similar files e.g. Many repeating sequences of a certain type should be examined: abcabc May vary from file to file

15. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Hardware Support for Runlength Initially latch in base Down counter indicates number of strides to take. Offset used to augment initial base Fairly simple to implement.

16. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Hardware for Lempel-Ziv Down counter stores stride length Register window holds repeated data Pointer extracts appropriate data value. Last symbol included when count is 0

17. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Results Compression ratio measures amount of compression from original data stream Adaptive reorder is most effective Last column is wild card approach, compares favorably with other approaches

18. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Configuration Cloning Configuration can be transferred from one place to another Program one cell, copy to others inside array.

19. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Cloning Benefits Fast reconfiguration time Low-power – reduced external I/O Scalable to large array sizes Might allow for fault tolerance

20. Lecture 18: Dynamic Reconfiguration II November 12, 2004 Summary A number of configuration modes exist for transferring data from source to FPGA Compression scheme like wild carding evaluation -> take advantage of 2D regularity to reduce data transfer times. Data compression in the form of data word encoding also effective. Configuration cloning avoids off-chip I/O by replicating configuration information already on device.