1. ILC Trigger & DAQ Issues - 1 ILC DAQ issues ILC DAQ issues By P. Le Dû Patrick.le-du@cea.fr

2. ILC Trigger & DAQ Issues - 2 Trigger concept  No hardware trigger ! Software Trigger concept  No hardware trigger ! Sub-Detectors FE Read-out Signal processing – digitization, no trigger interrupt Sparcification,cluster finding and/or data compression Buffering Sub-Detectors FE Read-out Signal processing – digitization, no trigger interrupt Sparcification,cluster finding and/or data compression Buffering Data Collection is triggered by every train crossing Trigger :Software Event Selection using partial information of a complete train (equivalent to L1) Select ‘Bunches Of Interest’ Event classification according to physics, calibration & machine needs (HLT) Data Collection is triggered by every train crossing Trigger :Software Event Selection using partial information of a complete train (equivalent to L1) Select ‘Bunches Of Interest’ Event classification according to physics, calibration & machine needs (HLT) Monitoring & on-line processing S1S2S3S4Sn 1 ms 200 ms Few sec Data streams Read-Out Buffer Network Detector Front End Processor Farm(s) Storage 3000 Hz Few Hz 1 MBytes Average event size Data Flow up to 1 ms active pipeline (full train) Dead time free

3. ILC Trigger & DAQ Issues - 3 ILC DAQ conceptual (GLD) Architecture VFD VTX ECAL TPC HCAL MUON PPPPPPPPPPPPPPPP Data Steams Logger and Mass Storage Event building Network 10-20 Gbit/sec Processor farm (one bunch train per processor) Event manager & Control Detector Buffering (per bunch train in Mbytes/BT = 140 MB/s) Links Select Bunch Of Interest (200 Hz) SiT Machine 1 G2.6 M5 M5K4568 K12K9215K 10k 5MB1MB 110 MB 20 MB3 MB1 MB 1GB/s = 100 PB/year

4. ILC Trigger & DAQ Issues - 4. About systems boundaries …..moving due to !  evolution of technologies,sociology ….. Subdetectors FE Read Out Signal processing Local FE Buffer Machine Synchronization Detector feedback Beam BT adjustment Data Collection (ex on-line) Bunch Train data collection from Buffer RO Bunch Of Interest selection SW trigger & algorithms Event Building Control - supervisor On line Processing Global calibration,monitoring and physics Local (temporary) Data logging (Disks) Full Integration of Machine DAQ In the data collection system NEW ! Global Detector Network (worlwide) Detector Integration Remote Control Rooms (3?) –Running modes Local stand alone Test Global RUN –Remote shifts Slow control Detector Monitoring Physics & data analysis (ex On- Off line) –Farms –GRID … Final Data storage Read out Node Partitionning (physical and logical) Read out Node Partitionning (physical and logical) Uniform interface

5. ILC Trigger & DAQ Issues - 5 Cosmic trigger ????? –Very useful during installation and debugging –Compatibility with power cycling ???? Clock, machine synchronization and timing distribution – with experts from LHC ! (Ph. Farthouat) Somes Issues To be discussed in specific meetings

6. ILC Trigger & DAQ Issues - 6 Current view of a uniform RO architecture Preampli Shaper Digitizer VTX CCD MAPS DEPFET ….. TRK Si TPC ECAL Si W Scint W HCAL Digital Analog Muon RPC Scint … VFD Sensor technology FPGA Receiver Digital Processing MUX RO Buffer Local Data Management GDNGDN Local/Global Controls & Services Partition Running mode (Stand alone, test, RUN) Synchronization & machine interface Databases : Calibration & Monitoring …… Integration To be studied! On detector Very Front End Local Signal Processing and buffer Common/uniform Interface Front End (On / Near detector) Commercial standardDedicated ASIC and/or SOC* Read Out Node/Hub *System On Chip Global Detector Network

7. ILC Trigger & DAQ Issues - 7 ILC ‘today’ Data Collection Network model Run Control Monitoring Histograms Event Display DCS Databases... Analysis Farm Mass storage Data logging Config Manager  Local/ worldwide Remote (GDN) Synchro NO On line – Off line boundary Local/Global Network(s) Wordlwide! Machine Bx BT feedback Local partition Data collection Sw triggers Sub Detector Read-Out Node FPGA receiver Buffer FPGA receiver Buffer FPGA receiver Buffer Proc receiver Buffer Data link(s)Services Networking Hub On/Near Detector Front End FPGA Direct network accessFrom Detectors Trigger Farms & Analysis Controls &Storage servers EVENT BUILDER NETWORK Multi Terabit/s

8. ILC Trigger & DAQ Issues - 8 Trigger & Event Analysis COMPUTING MODEL Sec. Temporary storage Monitoring Calibration Alignements Physics monitoring “Gold Platted“ events Physics samples Bunch Train Processing (ex L1) Database “Garbage” Final storage Candidates Storage Calibration Constants Sub-Detector performance “Analysis” farm Sample Prescale Compress Fast Analysis Stream Physics streams 200 ms Hours Days Year S1 S2 Sn Bunch Of Interest & classification Simple signatures : e/g, µ, taus,Jet Detector matching Complex signatures : PFA Missing Et, scalar Et Invariant and transverse mass separation … vertices, primary and displaced Selection: Thresholding Prescaling “Intelligent formatting “ Bunch train Software Trigger (equivalent to L1) using fast and/or simple information at the bunch level Machine Infos Event Classification (HLT) ON LINE OFF LINE 200 Hz

9. ILC Trigger & DAQ Issues - 9 Computing and communication trends 1000Gbit/I N 2 10Mbit/I N 2 2015 1Gbit/IN 2 Mass storage Bandwidth

10. ILC Trigger & DAQ Issues - 10 Read Out evolution LHC --> ILC Subdetector Read Out Crate (VME 9U) Read Out Driver Read Out Buffer (3 ROBin) ROS (150 PCs) Gbit Link to Gbe Switch (60 PCs) 92 SLink Subdetector 400 Robin (PCI) AMC ATCA Module ATCA Crate Digital Buffer  C  CTA

11. ILC Trigger & DAQ Issues - 11 What next Common work with Machine CTRL group –ATCA – GAN –(Slow) Controls Look for EUDET 2 ???? Workplans – ATCA experience – Global (Test beam) Detector networking Between DESY/CERN,FNAL/SLAC,KEK ????