1. Microelectronic Circuits - Fourth Edition Sedra/Smith 0 PowerPoint Overheads to Accompany Sedra/Smith Microelectronic Circuits 4/e ©1999 Oxford University Press.

2. Microelectronic Circuits - Fourth Edition Sedra/Smith 1 Fig. 13.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

3. Microelectronic Circuits - Fourth Edition Sedra/Smith 2 Fig. 13.3 Definitions of propagation delays and switching times of the logic inverter.

4. Microelectronic Circuits - Fourth Edition Sedra/Smith 3 Fig. 13.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

5. Microelectronic Circuits - Fourth Edition Sedra/Smith 4 Fig. 13.5 The voltage transfer characteristic (VTC) of the CMOS inverter when Q N and Q P are matched.

6. Microelectronic Circuits - Fourth Edition Sedra/Smith 5 Fig. 13.12 A two-input CMOS NOR gate.

7. Microelectronic Circuits - Fourth Edition Sedra/Smith 6 Fig. 13.13 A two-input CMOS NAND gate.

8. Microelectronic Circuits - Fourth Edition Sedra/Smith 7 Fig. 13.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) rations of Q N and Q P, respectively, of the basic inverter.

9. Microelectronic Circuits - Fourth Edition Sedra/Smith 8 Fig. 13.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) rations of Q N and Q P, respectively, of the basic inverter.

10. Microelectronic Circuits - Fourth Edition Sedra/Smith 9 Fig. 13.21 VTC for the pseudo-NMOS inverter. This curve is plotted for V DD = 5, V tn = -V tp = 1 V, and r = 9.

11. Microelectronic Circuits - Fourth Edition Sedra/Smith 10 Fig. 13.33 (a) basic structure of dynamic-MOS logic circuits; (b) waveform of the clock needed to operate the dynamic-logic circuit; and (c) an example circuit.

12. Microelectronic Circuits - Fourth Edition Sedra/Smith 11 Fig. 13.34 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static-power dissipation.

13. Microelectronic Circuits - Fourth Edition Sedra/Smith 12 Fig. 13.35 Two single-input dynamic-logic gates connected in cascade. With the input A high, during the evaluation phase C L2 will partially discharge and the output at Y 2 will fall lower than V DD, which can cause logic malfunction.

14. Microelectronic Circuits - Fourth Edition Sedra/Smith 13 Fig. 13.37 (a) Two single-input DOMINO CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.

15. Microelectronic Circuits - Fourth Edition Sedra/Smith 14 Fig. 13.38 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point of the latch.

16. Microelectronic Circuits - Fourth Edition Sedra/Smith 15 Fig. 13.40 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by .

17. Microelectronic Circuits - Fourth Edition Sedra/Smith 16 Fig. 13.42 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory chips.

18. Microelectronic Circuits - Fourth Edition Sedra/Smith 17 Fig. 13.44 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase nonoverlapping clock whose waveforms are shown in (b).

19. Microelectronic Circuits - Fourth Edition Sedra/Smith 18 Fig. 13.45 (a) A master-slave D flip-flop. Note that the switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required.

20. Microelectronic Circuits - Fourth Edition Sedra/Smith 19 Fig. 13.47 Monostable circuit using CMOS NOR gates. Signal source v I supplies the trigger pulses.

21. Microelectronic Circuits - Fourth Edition Sedra/Smith 20 Fig. 13.50 Timing diagram for the monostable circuit in Fig. 13.47.

22. Microelectronic Circuits - Fourth Edition Sedra/Smith 21 Fig. 13.52 (a) A simple astable multivibrator circuit using CMOS gates. (b) Waveforms for the astable circuit in (a). The diodes at the gate input are assumed ideal and thus limit the voltage v I1 to 0 and V DD.

23. Microelectronic Circuits - Fourth Edition Sedra/Smith 22 Fig. 13.53 (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/(6t p ).

24. Microelectronic Circuits - Fourth Edition Sedra/Smith 23 Fig. 13.54 A 2 M+N -bit memory chip organized as an array of 2 M rows x 2 N columns.

25. Microelectronic Circuits - Fourth Edition Sedra/Smith 24 Fig. 13.55 A CMOS SRAM memory cell.

26. Microelectronic Circuits - Fourth Edition Sedra/Smith 25 Fig. 13.60 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which can utilize both B and B lines). DRAMs can be turned into differential circuits by using the “dummy cell” arrangement shown in Fig. 13.61.

27. Microelectronic Circuits - Fourth Edition Sedra/Smith 26 Fig. 13.61 Waveforms of v B before and after activating the sense amplifier. In a read-1 operation, the sense amplifier causes the initial small increment  V(1) to grow exponentially to V DD. In a read-0 operation, the negative  V(0) grows to 0. Complementary signal waveforms develop on the B line.

28. Microelectronic Circuits - Fourth Edition Sedra/Smith 27 Fig. 13.62 Arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.

29. Microelectronic Circuits - Fourth Edition Sedra/Smith 28 Fig. 13.63 A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.

30. Microelectronic Circuits - Fourth Edition Sedra/Smith 29 Fig. 13.64 A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.

31. Microelectronic Circuits - Fourth Edition Sedra/Smith 30 Fig. 13.65 A free column decoder. Note that the colored path shows the transistors that are conducting when A 0 = 1, A 1 = 0, and A 2 = 1, the address that results in connecting B 5 to the data line.

32. Microelectronic Circuits - Fourth Edition Sedra/Smith 31 Fig. 13.66 A simple MOS ROM organized as 8 words x 4 bits.

33. Microelectronic Circuits - Fourth Edition Sedra/Smith 32 Fig. 13.67 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.

34. Microelectronic Circuits - Fourth Edition Sedra/Smith 33 Fig. 13.68 Illustrating the shift in the i D -v GS characteristic of a floating-gate transistor as a result of programming.

35. Microelectronic Circuits - Fourth Edition Sedra/Smith 34 Fig. 13.69 The floating-gate transistor during programming.

36. Microelectronic Circuits - Fourth Edition Sedra/Smith 35 Fig. 14.1 Switching times of the BJT in the simple inverter circuit of (a) when the input v 1 has the pulse waveform on (b). The effects of stored base charge following the return of v 1 to V 1 are explained in conjunction with Eqs. (14.2) and (14.3).

37. Microelectronic Circuits - Fourth Edition Sedra/Smith 36 Fig. 14.20 Analysis of the TTL gate with the input high. The circled numbers indicate the order of the analysis steps.

38. Microelectronic Circuits - Fourth Edition Sedra/Smith 37 Fig. 14.22 Analysis of the TTL gate when the input is low. The circled numbers indicate the order of the analysis steps.

39. Microelectronic Circuits - Fourth Edition Sedra/Smith 38 Fig. 14.23 The TTL gate and its voltage transfer characteristic.

40. Microelectronic Circuits - Fourth Edition Sedra/Smith 39 Fig. 14.24 The TTL NAND gate.

41. Microelectronic Circuits - Fourth Edition Sedra/Smith 40 Fig. 14.25 Structure of the multiemitter transistor Q 1.

42. Microelectronic Circuits - Fourth Edition Sedra/Smith 41 Fig. 14.28 A Schottky TTL (known as STTL) NAND gate.

43. Microelectronic Circuits - Fourth Edition Sedra/Smith 42 Fig. 14.33 Basic gate circuit of the ECL 10K family.

44. Microelectronic Circuits - Fourth Edition Sedra/Smith 43 Fig. 14.35 Simplified version of the ECL gate for the purpose of finding transfer characteristics.

45. Microelectronic Circuits - Fourth Edition Sedra/Smith 44 Fig. 14.36 The OR transfer characteristic v OR versus v 1, for the circuit in Fig. 14.35.

46. Microelectronic Circuits - Fourth Edition Sedra/Smith 45 Fig. 14.38 The NOR transfer characteristic, v NOR versus v 1, for the circuit in Fig. 14.35.

47. Microelectronic Circuits - Fourth Edition Sedra/Smith 46 Fig. 14.44 Development of the BiCMOS inverter circuit: (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each Q N and Q P of the CMOS inverter; (b) the circuit in (a) can be thought of as utilizing these composite devices; (c) to reduce the turn-off times of Q 1 and Q 2, “bleeder resistors” R 1 and R 2 are added; (d) implementation of the circuit in (e) using NMOS transistors to realize the resistors; (e) an improved version of the circuit in (c) obtained the lower end of R 1 to the output mode.