1. A Faster Satisfiability Model and Algorithm for Circuit Delay Computation 鍾逸亭

2. Outline Model introduction Arrival time information – Example Modified arrival time Comparasion with papers Future work

3. Model introduction (1/2) Floating mode sensitization – On-input can decide the final value of the gate. – On-input is the earliest controlling-value, or – On-input is the latest nc and side-inputs are nc. Viability mode sensitization – If a gate is stable no earlier than t (arrival ≧ t), – At least a fanin is stable no earlier than t-d, and – Either a fanin is stable no earlier than t-d or is nc. Two model have the same delay – Viability model has a simpler format On-input of AND = Earliest 0, or Latest 1, other are 1 0001101100011011

4. Model introduction (2/2) Viability model for circuit delay computation – We want to check whether circuit delay ≧ D – X is the TCF, X(p,D)=1 means arrival(p) ≧ D – For a X, it can be compute recursively 3(2+k) clauses – In fact, we only need to build the positive X model: 1+k clauses p Ex. Check D=2 g abab

5. arrival t 1 t 2 t 3 t max X( f, t)= 1 X(f,t 2 ) X(f,t 3 ) … 0 2 Arrival time information Arrival = 4, 6 X ≦ 4 = 1  Arrival must ≧ 4 X 5 = X 6  Arrival ≧ 5 means Arrival ≧ 6 X >6 = 0  Arrival cannot > 6 2 4

6. Example ABAB 111111 1. Compute all arrival time 2222 3 3,4 4,5 3,5,6 4,5,6,7 2. Construct TCF model for max delay=7 X7X7 X 6 =0 X 6 X 5 X 5 =0 X 4 =0 X 4 X 3 =1 X 3 =0 0000 arrival t 1 t 2 t 3 t max X( f, t)= 1 X(f,t 2 ) X(f,t 3 ) … 0 3. Apply SAT solver to make some X PO =1 #TCF = 4

7. Example ABAB 1. Compute all arrival time 2. Construct TCF model for max delay=7 X7X7 X6X6 X5X5 X4X4 1 3. Apply SAT solver to make some X PO =1 =1 0 1 0 1 1111 1 0 Conflict! Reduce max delay

8. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 ABAB 111111 2222 3 3,4 4,5 3,5,6 4,5,6,7 X6X6 X5X5X5X5 X 4 =1 X 4 =0 X 4 X 3 =1 X 3 =0 0000 arrival t 1 t 2 t 3 t max X( f, t)= 1 X(f,t 2 ) X(f,t 3 ) … 0 3. Apply SAT solver to make some X PO =1 #TCF = 4 Two cases

9. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 ABAB X6X6 X5X5 X4X4 1 3. Apply SAT solver to make some X PO =1 Case1: =1 0 0 1 1111 1 0 Conflict! =1

10. Example 1. Compute all arrival time 2. Construct TCF model for max delay=6 ABAB X6X6 X5X5 1 3. Apply SAT solver to make some X PO =1 Case2: =1 0 1 1111 1 0 Conflict! Reduce max delay

11. Example 1. Compute all arrival time 2. Construct TCF model for max delay=5 ABAB 111111 2222 3 3,4 4,5 3,5,6 4,5,6,7 X5X5 X 4 =1 X 4 X 3 =1 X 3 =0 0000 arrival t 1 t 2 t 3 t max X( f, t)= 1 X(f,t 2 ) X(f,t 3 ) … 0 3. Apply SAT solver to make some X PO =1 #TCF = 2

12. Example 1. Compute all arrival time 2. Construct TCF model for max delay=5 ABAB X5X5 1X41X4 1 arrival t 1 t 2 t 3 t max X( f, t)= 1 X(f,t 2 ) X(f,t 3 ) … 0 3. Apply SAT solver to make some X PO =1 Total # TCF = 10 =1 =1 or 0 0 01 SAT! 4. True delay = 5

13. True arrival time Modified arrival time ABAB 111111 2 3 3, 4 4, 5 3, 5, 6 4, 5, 6, 7 0000 1.There may be some false arrival time in the circuit. (Unit arrival time must be true, so we need not to check) 2.We can pick a cut of circuit and check the critical arrival time. 3.Then we can propagate new arrival time information to PO. 4.If X(PO, max delay) is UNSAT, repeat 2. 2 UNSAT X5X5 X 4 =1 X 4 =0 0 0 01 SAT! Total # TCF is reduced form 10 to 3.

14. Modified arrival time Cut Strategy: – Critical arrival time number <= cutLimit – Start from the level_num*ratio level – Offset CircuitSAT timeNew SAT time TCFNew TCF Final/total cutLimit, offset, ratio C75520.0010376168/38610, 1, 50 C62880.033995 948638/8891,100,80 C180.2479630.19797176044203/83462,10,50 C190.5259200.3809445453029028/446602,10,50

15. Comparasion with papers Model – floating-mode sensitization # TCF vars Run time

16. ANDOR [1] [2] Ours(Viability) Model-formulae

17. # Variables# Clauses [1] K+57K+8 [2] 22(K+1) Ours 1K+1 Model-cnf K-input gate

18. Circuit delay model# Clauses [1] 1 [2] 2 * PO + 1 Ours 1 Model-circuit delay

19. # Variables VARS[1][2]Ours c13555176.91590.2318.6 c19088846.82184.7285.7 c26705534.51824.1606.5 c354025317.95696.31890.4 c4326040.11323.9138.2 c4998349.42152.188.2 c531513282.84413.61214.4 c6288305594.963909.826109.2 c755223287.56499.31538 c8803707.81114.6145.9

20. Run time of SAT solver Time(s)[1][2]Ours c13550.050.020.002 c19080.140.040.001 c26700.050.020.003 c35400.270.050.006 c4320.060.020 c4990.10.030 c53150.170.050.006 c62887.161.30.226 c75520.350.060.008 c8800.030.010

21. Future Work How to find a better cut or … Find all true paths with delay >= D. Extend unit delay model to continuous model. Timing optimization needs what information?

22. Reference [1] Satisfiability Models and Algorithms for Circuit Delay Computation. Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira and Karem A. Sakallah. Cadence European Laboratories [2] Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. Yu-Min Kuo, Student Member, IEEE, Yue-Lung Chang, and Shih-Chieh Chang, Member, IEEE