1. Boolean Algebra and Logic Gates 1 Computer Engineering (Logic Circuits) Lec. # 8 (Combinational Logic Circuit) Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering Faculty of Engineering Zagazig University

2. Boolean Algebra and Logic Gates 2 http://www.tsgaafar.faculty.zu.edu.eg Email: tsgaafar@yahoo.com Course Web Page

3. Lec. # 8 Ch. 4 Combinational Logic Circuits (Contd.) Boolean Algebra and Logic Gates 3

4. 4 / 65 Binary Adder  Half Adder Adds 1-bit plus 1-bit Produces Sum and Carry HA xyxy SCSC x y C S 0 0 1 1 00 1 1 1 0 x + y ─── C S xyxy SCSC

5. 5 / 65 Binary Adder  Full Adder Adds 1-bit plus 1-bit plus 1-bit Produces Sum and Carry x y z C S 0 0 00 0 0 10 1 0 1 00 1 0 1 11 0 1 0 00 1 1 0 11 0 1 1 01 0 1 1 11 x + y + z ─── C S FA xyzxyz SCSC y 0101 x1010 z y 0010 x0111 z S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz

6. 6 / 65 Binary Adder  Full Adder xyzxyz SCSC xyzxyz SCSC S = xy'z'+x'yz'+x'y'z+xyz = x  y  z C = xy + xz + yz

7. 7 / 65 Binary Adder  Full Adder XyzXyz SCSC HA xyzxyz SCSC

8. 8 / 65 Binary Adder c3 c2 c1. + x3 x2 x1 x0 + y3 y2 y1 y0 ──────── Cy S3 S2 S1 S0 FA x3 x2 x1 x0 FA y3 y2 y1 y0 S3 S2 S1 S0 C4 C3 C2 C1 0 Binary Adder x3x2x1x0 y3y2y1y0 S3S2S1S0 C0 Cy Carry Propagate Addition

9. 9 / 65 Binary Adder  Carry Propagate Adder CPA A3 A2 A1 A0B3 B2 B1 B0 S3 S2 S1 S0 C0Cy CPA A3 A2 A1 A0B3 B2 B1 B0 S3 S2 S1 S0 C0Cy x3 x2 x1 x0 y3 y2 y1 y0 x7 x6 x5 x4 y7 y6 y5 y4 S3 S2 S1 S0S7 S6 S5 S4 0

10. 10 / 65 BCD Adder  4-bits plus 4-bits  Operands and Result: 0 to 9 + x3 x2 x1 x0 + y3 y2 y1 y0 ──────── Cy S3 S2 S1 S0 X +Y x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S 0 0 + 00 0 = 000 0 0 + 10 0 0 0 0 1= 100 0 0 1 0 + 20 0 0 0 1 0= 200 0 1 0 0 + 90 0 1 0 0 1= 901 0 0 1 1 + 00 0 0 10 0 = 100 0 0 1 1 + 10 0 0 1 = 200 0 1 0 1 + 80 0 0 11 0 0 0= 901 0 0 1 1 + 90 0 0 11 0 0 1= A01 0 2 + 00 0 1 00 0 = 200 0 1 0 9 + 91 0 0 1 = 1210 0 1 0 Invalid Code Wrong BCD Value 0001 1000

11. 11 / 65 BCD Adder X +Yx 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S 0 Required BCD OutputValue 9 + 01 0 0 10 0 = 901 0 0 10 0 0 0 1 0 0 1= 9 9 + 11 0 0 10 0 0 1= 1001 0 0 0 0 1 0 0 0 0= 16 9 + 21 0 0 10 0 1 0= 1101 0 1 10 0 0 1 = 17 9 + 31 0 0 10 0 1 1= 1201 1 0 00 0 0 1 0 0 1 0= 18 9 + 41 0 0 10 1 0 0= 1301 1 0 10 0 0 1 0 0 1 1= 19 9 + 51 0 0 10 1 = 1401 1 1 00 0 0 1 0 1 0 0= 20 9 + 61 0 0 10 1 1 0= 1501 1 0 0 0 1 0 1 0 1= 21 9 + 71 0 0 10 1 1 1 = 1610 0 0 0 0 1 0 1 1 0= 22 9 + 81 0 0 11 0 0 0 = 1710 0 0 10 0 0 1 0 1 1 1= 23 9 + 91 0 0 1 = 1810 0 1 00 0 0 1 1 0 0 0= 24 + 6 

12. 12 / 65 BCD Adder  Correct Binary Adder’s Output (+6) If the result is between ‘A’ and ‘F’ If Cy = 1 S 3 S 2 S 1 S 0 Err 0 0 0 1 0 0 00 1 0 0 10 1 0 1 1 0 1 11 1 1 0 01 1 1 0 11 1 1 1 01 1 1 1 S1S1 S2S2 S3S3 1111 11 S0S0 Err = S3 S2 + S3 S1

13. 13 / 65 BCD Adder Err

14. 14 / 65 Binary Subtractor  Use 2’s complement with binary adder x – y = x + (-y) = x + y’ + 1

15. 15 / 65 Binary Adder/Subtractor  M: Control Signal (Mode) M=0  F = x + y M=1  F = x – y

16. 16 / 65 Overflow  Unsigned Binary Numbers  2’s Complement Numbers FA x3 x2 x1 x0 FA y3 y2 y1 y0 S3 S2 S1 S0 C4 C3 C2 C1 0 Carry FA x3 x2 x1 x0 FA y3 y2 y1 y0 S3 S2 S1 S0 C4 C3 C2 C1 0 Overflow

17. 17 / 65 Magnitude Comparator  Compare 4-bit number to 4-bit number 3 Outputs: Expandable to more number of bits Magnitude Comparator A3A2A1A0 B3B2B1B0 A B

18. 18 / 65 Magnitude Comparator

19. 19 / 65 Magnitude Comparator A3 A2 A1 A0B3 B2 B1 B0 A B I(A>B) I(A=B) I(A<B) x3 x2 x1 x0 y3 y2 y1 y0 x7 x6 x5 x4 y7 y6 y5 y4 A B Magnitude Comparator A3 A2 A1 A0B3 B2 B1 B0 A B I(A>B) I(A=B) I(A<B) 010010

20. 20 / 65 Decoders  Extract “Information” from the code  Binary Decoder Example: 2-bit Binary Number Binary Decoder x1 x0 Only one lamp will turn on 0000 10001000

21. 21 / 65 Decoders  2-to-4 Line Decoder I 1 I 0 Y 3 Y 2 Y 1 Y 0 0 0 0 0 1 0 10 0 1 0 1 00 1 0 0 1 1 0 0 0 Binary Decoder I1 I0 y3 y2 y1 y0

22. 22 / 65 Decoders  3-to-8 Line Decoder Binary Decoder I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

23. 23 / 65 Decoders  “Enable” Control Binary Decoder I1 I0 E Y3 Y2 Y1 Y0 EI 1 I 0 Y 3 Y 2 Y 1 Y 0 0x 0 0 10 0 0 0 1 10 10 0 1 0 11 00 1 0 0 11 1 0 0 0

24. 24 / 65 Decoders  Expansion I 2 I 1 I 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 0 0 00 0 0 0 0 0 0 1 0 0 10 0 0 0 0 0 1 0 0 1 00 0 0 0 0 1 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 1 0 0 0 0 1 0 10 0 1 0 0 0 0 0 1 1 00 1 0 0 0 0 0 0 1 1 11 0 0 0 0 0 0 0 I2 I1 I0 Binary Decoder I0 I1 E Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder I0 I1 E Y3 Y2 Y1 Y0

25. Decoders  Active-High / Active-Low I 1 I 0 Y 3 Y 2 Y 1 Y 0 0 0 0 0 1 0 10 0 1 0 1 00 1 0 0 1 1 0 0 0 I 1 I 0 Y 3 Y 2 Y 1 Y 0 0 1 1 1 0 0 11 1 0 1 1 01 0 1 1 1 0 1 1 1 Binary Decoder I1 I0 Y3 Y2 Y1 Y0 Binary Decoder I1 I0 Y3 Y2 Y1 Y0

26. Implementation Using Decoders  Each output is a minterm  All minterms are produced  Sum the required minterms Example: Full Adder S(x, y, z) = ∑(1, 2, 4, 7) C(x, y, z) = ∑(3, 5, 6, 7) I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 x y z S C Binary Decoder

27. Implementation Using Decoders I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Binary Decoder x y z S C I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 x y z S C Binary Decoder