2. Fault models Stuck-at-0 00 11 Stuck-at-1 Reset coupling 0 0 Set coupling 11 00 1111 Inversion coupling 0 1 11 00 Transition  /0 0 1 Transition  /1 1 Transition  /1 ADRADR 0 0 Inversion coupling 1111 00 11 AND bridging 0 1 0000 1 0 OR bridging 1 0 OR bridging1111 Neighborhood pattern sensitive faults (active) 00 110011 11 0011 Neighborhood pattern sensitive faults (passive) 11 111100 00 00 Address decoder faults ADRADRADRADRADRADRADRADR

3. Elements of march test  (w0) xx xx xx xx xx xx xx xx 76 5 4 3 2 1 0 0  (r1,w0) 1 1 11 1 1 1 1 1 1 1 1 1 1 11  (w1)  (r0,w1) 00 0 0 0 0 0 0 00 0 0 00 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00 1 00 1 00 1 00 1 001 00 1 00 1 00 1 11 0 11 0 11 0 11 0 110 11 0 11 0 11 0

4. C - algorithm   Number of steps: 10n   Fault coverage: AFs, SAFs, TFs, CFins, CFids  (w0)  (r1,w0) 1 1 11 1 1 1 1 1 1 1 1 1 1 11  (r0,w1) 00 0 0 0 0 0 0 00 0 0 00 00 00 0 0 0 0 0 0 001 00 1 00 1 00 1 00 1 00 1 00 1 00 1 11 0 11 0 11 0 11 0 11 0 11 0 11 0 11 0  (r0,w1) 00 0 0 0 0 0 0 00 0 0 00 00 110 11 0 11 0 11 0 11 0 11 0 11 0 11 0  (r1,w0) 1 1 11 1 1 1 1 1 1 1 1 1 1 11 001 00 1 00 1 00 1 00 1 00 1 00 1 00 1  (r0) 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0

5. Checkerboard test and data retention  Designed to test refresh operations of DRAMs  Maximizes leakage current and detects leakage faults  Used as data retention test  To be effective it must consider address scrambling and layout 11001100 00110011 00110011 11001100

6. Data backgrounds for word memories   Multiple data backgrounds to detect coupling and bridging faults between cells of the same word   For every pair of cells all four combinations are checked   2 (log 2 w + 1) backgrounds   16 backgrounds for 128-bit wide memory   Normal and inverse   Multiple data backgrounds to detect coupling and bridging faults between cells of the same word   For every pair of cells all four combinations are checked   2 (log 2 w + 1) backgrounds   16 backgrounds for 128-bit wide memory   Normal and inverse D0D1D2D3D4D5D6D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

7. Data in word-oriented memory  (w0)  (r1,w0)  (r0,w1)  (r0,w1)

8. Parallel memory BIST  BISTmode Clock System logic Address generator FSMFSM Data generator Control generator Start Hold Done Fail Memory

9. Serial memory BIST System logic Data output Serial output Serial input Address M 0000 r00000 w1 1000 r01000 w11100 r01100 w11110 r01110 w11111 r11111  Minimal logic and routing  Longer test time Memory

10. Serial-parallel data interface trade-offs Memory MemoryMemory Memory

11. Memory BIST collar ++ Memory BIST controller controller To / From TAP controller Embedded memory BIST collar mux address / control bus and data linesmux address / control bus and data lines local comparator with single pass/faillocal comparator with single pass/fail local data generator to reduce routinglocal data generator to reduce routing area and timing problems local address validationlocal address validation Memory controller at the top level TAP controller as test engineTAP controller as test engine Memoryarray Functional logic

12. Shared controller and parallel test  Insert collars  Connect them through memory test bus to memory BIST controller to memory BIST controller to TAP to TAP ++ Memory BIST controller controller To / From TAP controller Memoryarray ++ Memoryarray Functional logic

13. Parallel memory BIST collar Memory array Data in Address Data out Ctrl MBIST mode   Sin Sout Clock = ? Functional address BIST address Functional data BIST data Pass / Fail BIST control Functional control

14. Full-Speed test application  Runs at system clock speeds with single cycle read/write operations  Uncovers speed-related defects  Reduce test application time. Addr/Cntrl/ Data Clock Memory Output Compare Circuitry Circuit Output Write Clock Cycle 1 Clock Cycle 2 Clock Cycle 3 Clock Cycle 4 Clock Cycle 5 Setup Read 1 Setup Write 1 Setup Read 2 Setup Read 3 Setup Write 2 Compare Read 1 Write 1 Read 2 Read 3 Compare Read 2 Pass/Fail Read 2 Pass/Fail Read 1 Compare Read 3 Read 1

15. Diagnostics  Detect failing location/data during test  Should diagnose speed related defects  Two types - Hold and resume, Hold and restart  How it works? BIST controller stops after 1 (or 2) failures Fail data is scanned out BIST session resumes from where it stops (Hold and resume) BIST session restarts after fail data is scanned out (Hold and restart)

16. Full-speed diagnostics ++ Memory array Memory array MBIST controller ATE Restart Diagnostic monitor

17. Yield improvement with memory redundancy  Memory percentage, defect rate, and redundancy amount affect yield Source: Zorian, Rodgers, DATE 2002 Redundancy Yield Improvement 0 10 20 30 40 50 60 70 80 90 100 0102030405060708090100 Chip Memory Percentage Memory Yield Optimal Level 3 Redundancy Level 2 Redundancy Level 1 Redundancy No Redundancy

18. ++ Memory BIST controller Memory BIST controller Memory Array Memory Array Redundancy and repair  Extra columns, rows, or rows and columns  At the end of test - good, repairable, or non-repairable  Repair data scanned out at the end of test

19. Full-Chip memory BIST integration Assign memories to controller (BIST Scheduling) Assign memories to controller (BIST Scheduling) Memory BIST Generation (Generate Controller/Collars) Memory BIST Generation (Generate Controller/Collars) BISTGENERATION Read in SOC netlist Identify memories Read in SOC netlist Identify memories Insert controllers in the design Stitch controllers to top-level Insert controllers in the design Stitch controllers to top-level BIST INSERTION

20. Full Chip Memory BIST Control Block BIST Block BIST Controller Memory 1 Memory 2 SOC TDO MBIST Data Register TDI CLK TM S TCK TRST TAP Controller rst_l test_h test_done fail_h Boundary Scan Register

21. Programmable algorithms  Selection of algorithms March1, March2, March3, Unique Address, Checkerboard, … March1, March2, March3, Unique Address, Checkerboard, … address jumping address jumping  Synthesizable algorithms user defined prior to synthesis user defined prior to synthesis simple language simple language number of sequences, backgrounds, sequence elements etc., number of sequences, backgrounds, sequence elements etc.,  Programmable algorithms defect mechanisms may not be known before fabrication defect mechanisms may not be known before fabrication memory BIST controller implements a class of algorithms memory BIST controller implements a class of algorithms field programmable parameters define active elements of test sequences

22. Summary Summary  Key components of a BIST controller algorithm controller data background generator address generator comparator  Very high quality test of embedded arrays  BIST controller shared across a number of memory arrays to reduce area  BIST diagnostics helps in gathering failure information  Built-in repair results in yield improvement