1. System Design with CoWare N2C - Overview

2. 2 Agenda q Overview –CoWare background and focus –Understanding current design flows –CoWare technology overview –Business & design results q Lunch q Technical introduction to CoWare N2C –Demos –Technical basics q Conclusion and Q&A

3. 3 CoWare background q Headquartered in Silicon Valley –American, European, and Asian offices –Growing quickly –EDA-experienced senior management –Venture capital funding in 1997 q Spun-off from IMEC in 1996 –Technology in development since 1992 –Ongoing R&D relationship with IMEC CoWare: The most complete tools and methodologies for system design, hardware-software co-design and IP re-use

4. 4 Convergence of Computing, Communication, & Consumer } } Software Hardware Time -to-Market Volume Revenue Profits Embedded Memory Analog Circuitry Digital Logic Embedded CPU Embedded DSP System-on-a-chip Glue software and hardware Market Focus: system design for SOC

5. 5 Complexity and convergence trends 64-bit RISC SPARC, MIPS R4xxx, MIPS VR10xxx... 32-bit RISC ARM7 & 9, ST-50/SH-5, SH-3, MIPS R3000… 16-bit micro M-core, x86… 8-bit micro 68HC05, 68HC11… Automotive Control Industrial Mil/Aero Consumer Computing Communications "C3"Applications Consumer Computing Communications "C3"Applications 10 5 10 7 10 8 10 9 10 6 10 0 10 3 10 2 10 1 10 4 Throughput (Clock Cycles) Cycles per Sample

6. 6 Americas Europe Asia Consumer Communication Semiconductor ---- Electronic Systems ---- SOC Key customers Matsushita

7. 7 Original Product Target Repainted to fit Reality Current system design process... System Level Integration Software Development Hardware Design IP Selection System Architecture Textual Specification

8. 8 Product Always On Target Executable Implementable Specification Design & Animation Mapping Onto Architecture Co-Design & Co-simulation Software Optimization Hardware Design Co-Implementation & Co-verification Language: C augmented with Structure & Concurrency Style: separation of Behavior & Communication Designing with CoWare N2C ™ Napkin-to-Chip™ 1 st time right In ½ the time ! Enables: Interface Synthesis™

9. 9 Impact of system design with CoWare N2C –Organizational impact - customer relationship q Higher-level sign-off : above RT-level q Availability of virtual prototypes for application developers / customers q Customer commitment moves forward in time Customer request Marketing/Architects HW design SW development HW/SW integration Design Implementation Customer commitment Customer request Marketing/Architects HW design SW development HW/SW integration Design Virtual Prototype Customer commitment Implementation Source: STMicroelectronics

10. 10 q "Chip-out" - the HW C Virtual Prototype –A software development platform –Multi-level reference design to… q Assess HW in end-application quickly q Map system functionality onto HW platform q Analyze architectures q Co-verify the implementation Two different CoWare N2C “use models” q "System-down" - the Napkin-to-Chip™ design flow –Executable and implementable specifications –HW-SW Co-design –Interface Synthesis –Architecture Analysis System ASSP System ASIC

11. 11 HW: what CoWare does Co-execute with Co-execute with HDL simulators HDL simulators HDL IP import HDL IP import Executable spec. Executable spec. Golden system Golden system testbench testbench Multiple model Multiple model levels levels Above RTL Below RTL Verification Design Synthesis Synthesis (e.g. Synopsys Design (e.g. Synopsys Design Compiler) Compiler) Deep-sub-micron Deep-sub-micron analysis analysis Physical design Physical design and doesn't do Executable and Executable and implementable implementable specification specification Interface Synthesis Interface Synthesis RTC & RTC2HDL RTC & RTC2HDL

12. 12 Import and profile Import and profile assembler code assembler code Verify with software Verify with software development tools development tools Executable spec. Executable spec. Golden system Golden system testbench testbench Multiple processor Multiple processor model levels model levels C-level Assembler level Verification Design Compilers Compilers RTOS synthesis RTOS synthesis and doesn't do Executable and Executable and implementable implementable specification specification Interface Synthesis Interface Synthesis Integrate with RTOS Integrate with RTOS Link and compile Link and compile SW: what CoWare does

13. 13 Make a 3-D change... System level Implementation level Verification Design HW SW Interface Synthesis Virtual Prototypes Executable implementable spec. …and increase interactivity throughout the design flow! Continuous refinement Multi-level models Above RTL Below RTL Verif. Design C-level Assembler level Verif. Design "Traditional" HW- SW Co-verification

14. 14 CoWare Methods & Tools System-on-a-chip success Digital Designers NORWAY Foundry System Integration BELGIUM Software Developers FRANCE End Customers A Powerline Modem System Company System Definition SWITZERLAND Utilities Source: Alcatel Microelectronics

15. 15 You and your customers can... Old way misses the target q Use executable specifications to –Share information without ambiguity –Get SW and HW teams working together q Use interface synthesis to –Explore design architecture alternatives –Ease design of product derivatives or new product generations q Use virtual prototypes to –Review & exchange product concepts –Get HW out of the SW critical path CoWare Napkin-to-Chip

16. 16 It’s time to move up again ! Netlist 7070 8282 8888 9797 Design RTL Mask Netlist Schematic Netlist RTL CoWare N2C C-Based System-Level Design Implementation