1. 1 COSC 3P92 Cosc 3P92 Week 1 Lecture slides Psychiatrist to patient "You have nothing to worry about - anyone who can pay my bill is certainly not a failure."

2. 2 COSC 3P92 Class Room Ground Rules Cell Phones My contact times –Open Door Policy –Email bockusd@brocku.ca

3. 3 COSC 3P92 Basics introduction, overview of basic architecture circuits, microprocessor chips microprogramming - CPU, ALU memory - chips, cache, virtual input/output instruction sets Advanced RISC vs CISC parallel computers special applications Course Overview

4. 4 COSC 3P92 Introduction computer: mechanism which processes information based on a predefined sequence of instructions digital computer: based on counting (base 2) analog computer: based on measurements (voltage thresholds) see text sections 1.3, 1.5 for history first stored-program computer proposed by John von Neumann (1945) - instructions interpreted sequentially - binary representation of data - typical von Neumann architecture

5. 5 COSC 3P92 1. CPU organization registers ALU input registers ALU A + B AB ALU output register

6. 6 COSC 3P92 CPU organization ALU - arithmetic logic unit - add, subtract, AND,... - often supplemented by floating-pt processors instructions: 1 - register-register 2 - register-memory 3 - memory-memory

7. 7 COSC 3P92 2. Memory organization: bits (0,1) byte (8 bits) word (1,2,4,... bytes) "boards" (1 megabyte) addressing: normally by byte address (convention) - “address alignment” word size is a measure of CPU power, but address and data path size between CPU and memory is a crucial factor main memory: hardware memory, usually chips secondary memory: external cheap storage (hard discs, floppies,...)

8. 8 COSC 3P92 3. Input Output device secondary storage (hard discs, floppies, tapes,...) interactive devices (terminals, mice,...) paper output (printers, plotters, FAX machines...) modems cable modems CD ROMS

9. 9 COSC 3P92 An execution cycle Control Unit Arithmetic Logic Unit Registers CPU (CU+Mem+Reg) An instruction cycle Fetch Decode Execute (CU) (CU+ALU+Reg+Mem+IO) Instruction cycle steps: 1. Fetch –the control unit reads an instruction from memory; 2. Decode –control unit decodes the instruction based on its internal logic; 3. Execute –depending the operation code (opcode) of the instruction, it enables the control signals to the ALU and/or the Input/Output devices to perform the required operation. (M.Cheng)

10. 10 COSC 3P92 Execution cycle The control unit interprets instructions, and is either hardwired or microprogrammed. registers include: program counter, instruction register, effective address register, accumulator and/or set of general-purpose registers. Arithmetic Logic Unit (ALU) performs basic binary addition, shift, and comparison operations. More advanced ones do multiplication, division, and floating-point operations. When an instruction is being decoded, operand(s) (the data) may have to be prefetched as well. Data path cycle: running (2) operands through the ALU and storing the result of central importance to CPU design

11. 11 COSC 3P92 Basics A CPU is an instruction sequencer and executor. - different CPU’s have different instruction sets A set of high-speed registers is incorporated into the CPU to assist instruction execution. PC (program counter) IR (instruction register) EAR (effective address register) MBR (memory buffer register) A simple (one-address) instruction executor can be defined as follows. LOOP EAR := EffectiveAddressOf( PC ); IR := MBR; PC := PC + 1; EAR := EffectiveAddressOf( Operand( IR ) ); Execute( OpCode( IR ), MBR ); END

12. 12 COSC 3P92 Basics The Program Counter holds the address of the next instruction to be executed. The Instruction Register holds the current instruction. On many modern processors, there is a distinction between a logical and a physical (or effective) address. Once the physical address of a memory word is calculated and loaded into the Effective Address Register, the content of the word is retrieved from memory to the Memory Buffer Register. Note that the execution processor can be implemented in 2 ways: 1. Hardware: direct instn execution 2. Interpreted: indirect instn execution also, hybrid methods that use both h/w and interpretation

13. 13 COSC 3P92 Conceptual Layers of a Modern Computer High-level language layer Assembly language layer Machine language layer Micro-instruction layer directly executed interpreted assembled compiled Hardware layer Hardware Application layer Operating System (M.Cheng)

14. 14 COSC 3P92 Classes of Computers Control Unit ALU instruction stream data stream Single-Instruction-Single-Data stream (SISD) Control Unit instruction stream ALU data stream 1 ALU data stream N Single-Instruction-Multiple-Data stream (SIMD)

15. 15 COSC 3P92 Classes of Computers. Control Unit instruction stream 1 ALU Control Unit instruction stream N data stream Multiple-Instruction-Single-Data stream (MISD) Control Unit ALU instruction stream 1 data stream 1 Control Unit ALU instruction stream N data stream N Multiple-Instruction-Multiple-Data stream (MIMD) (M.Cheng)

16. 16 COSC 3P92 Classes of Computers SISD: conventional serial computer. SIMD: vector processor - each instruction operates on a data vector rather than a single operand, e.g. CRAY MISD computer in general does not exist. But for reliability reason, there are computer systems with redundant processors which executes the same input by several independent processors. MIMD computer is actually called a multiprocessor, e.g, C.mmp at CMU.

17. 17 COSC 3P92 Basics Three different types of bus used to interconnect the CPU, memory and I/O devices. Control bus ( bidirectional )–carries the necessary commands and control signals to the various parts of the system. Address bus ( unidirectional )–specifies the address of the memory word or I/O device that the CPU wants to communicate. Data bus ( bidirectional )–carries the data transmitted between CPU, memory and I/O devices. MBR Registers ALU Address Bus Data Bus PC IR EAR CU Control Bus (To Memory or I/O Devices) (M.Cheng)

18. 18 COSC 3P92 Basics. If a computer has an N-bit address bus, then it can address up to 2**N unique locations. Every addressable unit may be of different sizes from one computer to another. It may be bit-addressable (e.g., Burroughs B1700), byte- addressable (e.g., Intel 8086), or word-addressable. (Note: There is no general agreement what a word size should be.) When we speak of a computer of size N-bit, we usually refer to the size of its data bus. It is possible to have an 8-bit computer with word size 16-bit (e.g., Intel 8088, Motorola 6800).

19. 19 COSC 3P92 Computer Structures General register machine - A two-address instruction: ADD X, Y % Y := Y + X; where X,Y and Z refer to a memory location or a register. - A three-address instruction: ADD X, Y, Z % Z := X + Y; - The CPU contains a set of general purpose (scratch-pad) registers. - Typically, this type of processors supports two-address or three-address instructions. - e.g., Motorola MC68000, DEC VAX-11, IBM 360

20. 20 COSC 3P92 Computer Structures Accumulator machine - e.g., Rockwell 6502, Motorola 6809 or 6800 series - There are one (or more) accumulators: general scratch-pad registers - all data processing instructions refer to at least one accumulator, hence one- address instructions of the form: LDA X % ACC := X; ADD X % ACC := ACC + X; where X refers to a memory location.

21. 21 COSC 3P92 Computer Structures Stack machine - A zero-address instruction has the following form: PUSH X % ++SP; *SP := X; POP X % X := *SP; - - SP; ADD % - - SP; *SP := *(SP+1) + *SP; SUB % - - SP; *SP := *(SP+1) - *SP; where X refers to a memory location. - e.g., Hewlett-Packard HP3000, Burroughs B1700 - All instructions are assumed to operate on the top of a LIFO stack data structure - A dedicated register, called stack pointer (SP), refers to the top of the stack. - All instructions must refer to the stack pointer implicitly, hence zero-address instructions. - Different instructions result in different amount to be added to or subtracted from the SP automatically.

22. 22 COSC 3P92 Types of Computers Midicomputer Supercomputer Maxicomputer - e.g. CRAY - usually SIMD - e.g.,CDC7600, IBM 370 - “ mainframe computer” - e.g.,DEC VAX 8600, IBM 4381, high-end SGI’s (?) - “supermini computer” Minicomputer -e.g.,higher-end Sun’s & SGI’s, DEC PDP-11 (16-bit), Data General NOVA -classification is obsolete Microcomputer e.g., IBM PC’s, Apple Macintosh, Amiga, Atari, SGI, Sun Cell phones, Pads, iPod etc. are the next generation of micro computers. fuzzy area

23. 23 COSC 3P92 Design goals for computer architectures performance - raw speed eg. MIPS, MFLOPS - speed with respect to a particular application, programming language or environment e.g., digital signal processing, FORTRAN, ADA, Prolog, Graphics, real-time systems Compatibility - with previous versions; other hardware & standards - with future versions

24. 24 COSC 3P92 Design goals for computer architectures. ease of use - easy to program e.g., instruction set, interaction with external devices - easy to add peripherals e.g., high-speed optical disks, a communication switching network

25. 25 COSC 3P92 Von Neumann memory (store) CPU Input/Output unit control addr data

26. 26 COSC 3P92 The end