1. IT 252 Computer Organization and Architecture Introduction Chia-Chi Teng

2. What is computer architecture about? Computer architecture is the study of building computer systems. IT 252 is roughly split into four parts. – First, we will discusses instruction set architectures—the bridge between hardware and software. – Second, we introduce more advanced processor implementations. The focus is on pipelining, which is one of the most important ways to improve performance. – Next, we talk about memory systems, I/O, and how to connect it all together. – We will also introduce you to Assembly and C programming through out the course.

3. Why should you care? It is interesting. – You will learn how a processor actually works! It will help you be a better programmer. – Understanding how your program is translated to assembly code lets you reason about correctness and performance. – Demystify the seemingly arbitrary (e.g., bus errors, segmentation faults) Many cool jobs require an understanding of computer architecture. – The cutting edge is often pushing computers to their limits. – Supercomputing, games, portable devices, etc. Computer architecture illustrates many fundamental ideas in all computing discipline. – Abstraction, caching, and indirection …

4. Personnel  Lecturer —Prof. Chia-Chi Teng ccteng@byu.edu —Office hours T/Th 9-11 Or by appointment  TA —Gary McGregor garymc@byu.net —Office hours T F  Course webpage: http://it252.groups.et.byu.net/11wi/IT252.php http://it252.groups.et.byu.net/11wi/IT252.php

5. Administrivia The textbooks provides the most comprehensive coverage – "Computer Systems: A Programmer's Perspective" 2nd Edition, by Randal E. Bryant & David R. O'Hallaron – The C Programming Language, Kernighan & Ritchie, 2 nd ed. Read the text prior to class class will supplement rather than regurgitate the text IT curriculum changes in Fall 2010 IT 251 (4) -> IT 252 (3) IT 104B (2) -> CS/ECEn 124 (3) IT 104A (2) -> part of IT 327 (4) Did you take 104 or 124?

6. Grading Professionalism: Attendance, Attitude, Participation, 5% final grade Homework – Usually due on every Friday and Monday, check course website often for detail and update, 25% final grade Quizzes - about 6 – 8, take home, 10 pts each, 15% final grade Lab reports – Due date to be specified by TA, 25% final grade Exams - final and at least one mid-term; usually open-book, take home, untimed 30%

7. Homework Homework exercises provide added impetus to keep up with the reading. Textbook problems Assignments are listed on course web page by weeks, usually due on Friday and the following Monday. Turn in: on blackboard AND in paper. Homework locker. We really want to encourage discussion, both in class and in lab. But zero tolerance for cheating, don’t go there. Don’t look for solutions online.

8. Labs  No lab this week. Lab 1 next week.  Room 335 —Hardware Description Language (VHDL), CPU design  Room 365 —Memory system, I/O …  Lab report: TA will give you detail

9. To-Do list Read chapter 1 before Thursday please read the entire course web thoroughly, today Course web is work in progress, please check back often make sure you’re on the IT 252 blackboard email list, and check your email daily keep up with the reading: this week … homework due – Check website lab report due – TA discretion via blackboard

10. What is Computer Architecture? It’s the study of the ___________ of computers  Structure: static arrangement of the parts  Organization: dynamic interaction of the parts and their control  Implementation: design of specific building blocks  Performance: behavioral study of the system or of some of its components 10/18/201510

11. Another definition: Instruction Set Architecture (ISA) Architecture is an interface between layers ISA is the interface between hardware and software ISA is what is visible to the programmer (and ISA might be different for OS and applications) ISA consists of: – instructions (operations and how they are encoded) – information units (size, how they are addressed etc.) – registers (or more generally processor state) – input-output control 10/18/201511

12. Computer structure: Von Neumann model 10/18/201512 Memory hierarchy I/OcontrolALU Registers PC state Memory bus I/O bus CPU Data path+ Control

13. Computer Organization Organization and architecture often used as synonyms Organization (in this course) refers to: – what are the basic blocks of a computer system, more specifically basic blocks of the CPU basic blocks of the memory hierarchy – how are the basic blocks designed, controlled, connected? Organization used to be transparent to the ISA. Today more and more of the ISA is “exposed” to the user/compiler. 10/18/201513

14. Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time). Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. – 2300 transistors, 1 MHz clock (Intel 4004) - 1971 – 16 Million transistors (Ultra Sparc III) – 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 – 55 Million transistors, 3 GHz, 130nm technology, 250mm 2 die (Intel Pentium 4) - 2004 – 140 Million transistor (HP PA-8500)

15. Illustration of Moore’s Law

16. Power Dissipation 10/18/201516

17. Evolution of Intel Microprocessor Speeds 10/18/201517 How about today?

18. POLL  Which type of CPU has the largest worldwide market share? —Intel —AMD —ARM —MIPS  http://www.polleverywhere.com/multipl e_choice_polls/LTE2OTY2MjI http://www.polleverywhere.com/multipl e_choice_polls/LTE2OTY2MjI

19. Where is the Market? Millions of Computers

20. ISA Type Sales What’s in your cell phone? Millions of Processor

21. Processor Performance Increase SUN-4/260MIPS M/120 MIPS M2000 IBM RS6000 HP 9000/750 DEC AXP/500 IBM POWER 100 DEC Alpha 4/266 DEC Alpha 5/500 DEC Alpha 21264/600 DEC Alpha 5/300 DEC Alpha 21264A/667 Intel Xeon/2000 Intel Pentium 4/3000

22. DRAM Capacity Growth 16K 64K 256K 1M 4M 16M 64M 128M 256M 512M

23. Impacts of Advancing Technology Processor – logic capacity:increases about 30% per year – performance:2x every 1.5 years Memory – DRAM capacity:4x every 3 years, now 2x every 2 years – memory speed:1.5x every 10 years – cost per bit:decreases about 25% per year Disk – capacity:increases about 60% per year ClockCycle = 1/ClockRate 500 MHz ClockRate = 2 nsec ClockCycle 1 GHz ClockRate = 1 nsec ClockCycle 4 GHz ClockRate = 250 psec ClockCycle

24. Example Machine Organization Workstation design target – 25% of cost on processor – 25% of cost on memory (minimum memory size) – Rest on I/O devices, power supplies, box CPU Computer Control Datapath MemoryDevices Input Output

25. PC Motherboard Closeup

26. Inside the Pentium 4 Processor Chip

27. Some Computer families Computers that have the same (or very similar) ISA – Compatibility of software between various implementations IBM – 704, 709, 70xx etc.. From 1955 till 1965 – 360, 370, 43xx, 33xx From 1965 to the present – Power PC DEC – PDP-11, VAX From 1970 till 1985 – Alpha (now Compaq, now HP) in 1990’s 10/18/201527

28. More computer families Intel – Early micros 40xx in early 70’s – x86 (086,…,486, Pentium, Pentium Pro, Pentium 3, Pentium 4) from 1980 on – IA-64 (Itanium) in 2001 SUN – Sparc, Ultra Sparc 1985 0n MIPS-SGI – Mips 2000, 3000, 4400, 10000 from 1985 on – CISC vs RISC – Complex Instruction Set vs Reduced Instruction Set – What is an instruction? 10/18/201528

29. Where Are We Now? CS142 & 124 IT344

30. MIPS is a RISC RISC = Reduced Instruction Set Computer R could also stand for “regular” All arithmetic-logical instructions are of the form MIPS (as all RISC’s) is a Load-Store architecture – ALU operates only on operands that are in registers – The only instructions accessing memory are load and store 10/18/201530

31. Registers Registers are the “bricks” of the CPU Registers are an essential part of the ISA – Visible to the hardware and to the programmer Registers are – Used for high speed storage for operands. For example, if variables i,j are in registers ax,cx respectively add ax,cx # i = i + j – Easy to name (most computers have limited number of registers visible to the programmer) – Used for addressing memory 10/18/201531

32. Registers (ct’d) Not all registers are “equal” – Some are special-purpose (e.g. program counter, stack pointer) – Some are used for integer and some for floating-point – Some have restricted use by convention 10/18/201532

33. Memory system  Memory is a hierarchy of devices with faster and more expensive ones closer to CPU —Registers —Caches (hierarchy: on-chip, off-chip) —Main memory (DRAM) —Secondary memory (disks) 10/18/2015CSE378 Gen. Intro33

34. Information units  Basic unit is the bit (has value 0 or 1)  Bits are grouped together in units and operated on together: —Byte = 8 bits —Word = 2 or 4 bytes —Double word = 2 words —Etc.  Integer: usually 4 bytes 10/18/2015CSE378 Gen. Intro34

35. Memory addressing Memory is an array of information units – Each unit has the same size – Each unit has its own address – Address of an unit and contents of the unit at that address are different 10/18/201535 address 0 1 2 -123 17 0 contents

36. Addressing In most of today’s computers, the basic unit that can be addressed is a byte. (how many bit is a byte?) – MIPS (and pretty much all CPU today) is byte addressable The address space is the set of all memory units that a program can reference – The address space is usually tied to the length of the registers – Intel 384/486/Pentium has 32-bit registers. Hence its basic address space is 4G bytes – MIPS has 32-bit registers. – Older micros (minis) had 16-bit registers, hence 64 KB address space (too small) – Some current (Intel CoreX, Alpha, Itanium, Sparc, Altheon) machines have 64-bit registers, hence an enormous address space 10/18/201536

37. Addressing words  Although machines are byte-addressable, 4 byte integers are the most commonly used units  Every 32-bit word starts at an address divisible by 4 10/18/201537 int at address 0 int at address 4 int at address 8

38. Big-endian vs. little-endian  Byte order within an int: 10/18/201538 0 0 123 123 Little-endian (we’ll use this) Big-endian 0 1 2 Memory address 3 int #0 byte int #0

39. The CPU - Instruction Execution Cycle  The CPU executes a program by repeatedly following this cycle 1. Fetch the next instruction, say instruction i 2. Execute instruction i 3. Compute address of the next instruction, say j 4. Go back to step 1  Of course we’ll optimize this but it’s the basic concept 10/18/201539

40. What’s in an instruction? An instruction tells the CPU – the operation to be performed via the OPCODE – where to find the operands (source and destination) For a given instruction, the ISA specifies – what the OPCODE means (semantics) – how many operands are required and their types, sizes etc.(syntax) Operand is either – register (integer, floating-point, PC) – a memory address – a constant 10/18/201540