1. Fall 2006 1 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Computer Organization Lecture 7 ALU design MIPS data path

2. Fall 2006 2 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering ALU design with LS181’s Assume –12-bit computer –Active high operands Must cascade three devices –Carry out must drive next carry in –Mode and select bused to all devices

3. Fall 2006 3 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering One device NOTE: Active low symbol provided

4. Fall 2006 4 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering ALU 12-bit design

5. Fall 2006 5 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Add operations What is the propagation time? Is it the same for all numbers? NOTE: S = 9, M = 0

6. Fall 2006 6 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Or operations What is (0x555) or’d (0xaaa)? NOTE: S = e, M = 1

7. Fall 2006 7 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Project 2 overview Sixteen-bit ALU Use four LS181 plus some other logic Arithmetic: +, - Logical: –and, or –shift left, shift right

8. Fall 2006 8 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Project 2 hints Use four LS181’s ALU Design shifter circuits Use muxes to select between ALU and shifters Design combinational logic to control muxes: consider a ROM

9. Fall 2006 9 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering ROM device bit 0 bit 7

10. Fall 2006 10 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Project 2 questions?

11. Fall 2006 11 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Shifting operations Goal: shift n-bit number left and right Definition: 1-bit shift –Left: lsb = 0, else bit n = bit n-1 –Right: msb = 0, else bit n = bit n+1 General function is to shifts n-bits

12. Fall 2006 12 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Shift left circuit Could you design a right shifter?

13. Fall 2006 13 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Timing What mathematical function does sll perform?

14. Fall 2006 14 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Major Computer Components Five classic computer components

15. Fall 2006 15 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Computer Components Input: receives information from external world Output: transmits information to external world Memory: holds programs and data Data path: physical route that carries info Control: coordinates overall flow of info Denoted Processor

16. Fall 2006 16 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering MIPS datapath overview Instruction read from memory Registers selected for operation ALU performs function Result written to register

17. Fall 2006 17 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Instruction fetch PC reset on power-up; e.g., 0x 0000 0000 PC clocked at some rate (~3.0 GHz today) Instructions (usually) accessed sequentially PC Instruction memory Read address Instruction 4 Add 32-bit number or instruction Incremented by 4 for word alignment

18. Fall 2006 18 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Register file Contains –Thirty-two, one-word numbers or registers (32 by 32, D-type flip-flops) –Similar to a small memory Registers: denoted $0 - $31, alternate names too Operations –Read any two registers –Write to one register

19. Fall 2006 19 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Register file symbol Two read ports, one write port NOTE: Orange denotes control signal 32

20. Fall 2006 20 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering R-format structure Instruction fields (rs, rt, rd) select registers and ALU operation (funct) Result written back into register file rs rt rd 32 funct Size 6 bits5 bits 6 bits R typeoprsrtrdshamtfunct

21. Fall 2006 21 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the registers and operation? Inst = 0x00430820 =0000 0000 0100 0011 0000 1000 0010 0000 $2 $3 $1 add

22. Fall 2006 22 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering I-format structure: lw & sw Requirements –Calculate effective address (addition) –Perform load (read) or store (write) Components –Register file –ALU for effective address –Data memory

23. Fall 2006 23 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering I-type EA review Examples –lw $t1, offset ($t2) –sw $t1, offset ($t2) Effective address (EA) calculation –adr = base + offset –adr = $t2 + Instr 15-0  32-bit added to 16-bit ?? Register $t1 (destination/load, source/store)

24. Fall 2006 24 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Memory reference logic Effective address = sum of (reg + immed) 5 32 5 5 rs rt immed add Size 6 bits5 bits 16 bits I typeoprsrtaddress/immediate

25. Fall 2006 25 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Design sign extension?

26. Fall 2006 26 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the registers and immed? 5 32 5 5 $2 $1 0x0064 add Instr = 0x8c410064 =1000 1100 0100 0001 0000 0000 0110 0100

27. Fall 2006 27 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering I-format structure: beq Example: beq $t1, $t2, offset –If $t1=$t2, then EA = PC + offset  branch taken –If $t1  $t2, then EA = PC  branch not taken Branch address –PC must first be incremented –Offset is word-aligned or shifted left 2 bits Conditional jump instruction

28. Fall 2006 28 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Beq instruction Requirements –Determine if two registers are equal (sub or compare) –Calculate the branch/jump address Components –Register file –Adder to increment PC –ALU for branch address

29. Fall 2006 29 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Branching logic ALU tests for zero Adder determines branch address rs rt immed Size 6 bits5 bits 16 bits I typeoprsrtaddress/immediate

30. Fall 2006 30 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the regs & sign extend? inst = 0x114cfff0 $0xa $0xc 0xfff0 0001 0001 0100 1100 1111 1111 1111 0000

31. Fall 2006 31 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering

32. Fall 2006 32 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the registers and operation? Inst = 0x00430820 0000 0000 0100 0011 0000 1000 0010 0000 $2 $3 $1 add rs rt rd func

33. Fall 2006 33 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Design sign extention?

34. Fall 2006 34 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the registers and immed? 5 32 5 5 $2 $1 0x0064 add Instr = 0x8c410064 1000 1100 0100 0001 0000 0000 0110 0100 lw$1, 100($2) rs rt immed

35. Fall 2006 35 EE 333 Lillevik 333f06-l7 University of Portland School of Engineering Find the regs and sign extend? inst = 0x114cfff0 $10 $12 immed = -16 000100 01010 01100 1111 1111 1111 0000 inst = 0001 0001 0100 1100 1111 1111 1111 0000 rs rt immed