1. Chap. 9 Instruction Set Architecture

2. Computer Architecture Concepts Instruction format –Opcode field Specify the operation to be performed –Address field Provide either a memory address or an address for selecting a processor register –Mode field Specify the way the address field is to be interpreted

3. Computer Architecture Concepts Basic computer operation cycle –Fetch the instruction from memory into a control register –Decode the instruction –Locate the operands used by the instruction –Fetch operands from memory (if necessary) –Execute the operation in processor registers –Store the results in the proper place –Go back to step 1 to fetch the next instruction

4. Computer Architecture Concepts Register Set –All registers in the CPU that are accessible to the programmer Mentioned in assembly lang. cf) register file for  -program, pipeline registers –Ex) Processor status register (PSR) –C, N, V, and Z from ALU Stack pointer (SP)

5. Operand Addressing Fetching operand within instruction –Implied address vs. explicit address The number of explicitly addressed operands per instruction –Three-address instructions –Two-address instructions –One-address instructions –Zero-address instructions long instructions Many steps of executions

6. Operand Addressing Three-address Instructions –Memory-to-memory architecture –Ex) X=(A+B)(C+D) ADD T1, A, BM[T1]  M[A]+M[B] ADD T2, C, DM[T2]  M[C]+M[D] MUL X, T1, T2M[X]  M[T1]+M[T2] ADD R1, A, BR1  M[A]+M[B] ADD R2, C, DR2  M[C]+M[D] MUL X, R1, R2M[X]  R1+R2

7. Operand Addressing Three-address Instructions –register-to-register (load/store) architecture Allow only one memory address –“load”, “store” instructions –Ex) X=(A+B)(C+D) LDR1,AR1  M[A] LDR2,BR2  M[B] ADDR3,R1,R2R3  R1+R2 LDR1,CR1  M[C] LDR2,DR2  M[D] ADDR1,R1,R2R1  R1+R2 MULR1,R1,R3R1  R1*R3 STX,R1M[X]  R1

8. Operand Addressing Two-address Instructions –Ex) X=(A+B)(C+D) MOVE T1, AM[T1]  M[A] ADD T1,BM[T1]  M[T1]+M[B] MOVE X,CM[X]  M[C] ADD X,DM[X]  M[X]+M[D] MUL X,T1M[X]  M[X]+M[T1] –If register-memory architecture ADD R1,AR1  R1+M[A]

9. Operand Addressing One-address Instructions –Single-accumulator architecture A special register called “accumulator” for obtaining one of the operands and as the location of the result –Ex) X=(A+B)(C+D) LDAACC  M[A] ADD BACC  ACC+M[B] STXM[X]  ACC LDCACC  M[C] ADDDACC  ACC+M[D] MULXACC  ACC*M[X] STXM[X]  ACC

10. Operand Addressing Zero-address Instructions –Stack architecture –Ex) X=(A+B)(C+D) PUSH ATOS  M[A] PUSH BTOS  M[B] ADDTOS  TOS+TOS-1 PUSH CTOS  M[C] PUSH DTOS  M[D] ADDTOS  TOS+TOS-1 MULTOS  TOS*TOS-1 POP XM[X]  TOS

11. Stack architecture Processing expressions –Postfix expression reverse Polish notation (RPN) Ex) (A+B)*C+(D*E)  A B + C * D E * + 3 12

12. Stack architecture –Program for evaluating “ A B + C * D E * + ” PUSH A PUSH B ADD PUSH C MUL PUSH D PUSH E MUL ADD

13. Addressing Modes Implied mode Immediate mode Register and register-indirect mode Direct addressing mode Indirect addressing mode Relative addressing mode Indexed addressing mode Base-register mode

14. Addressing Modes Implied mode –The operand is specified implicitly in the definition of the opcode. Immediate mode –The actual operand is specified in the instruction itself.

15. Addressing Modes Register-indirect mode –For addressing each of elements in arrays –Ex) ADD (R1)+, 3 M[R1]  M[R1]+3, R1  R1+1

16. Addressing Modes Direct addressing mode

17. Addressing Modes Indirect addressing mode –Addr. Field of instruction Address at which the effective addr. is stored in memory If indirect mode, …

18. Addressing Modes Indexed addressing mode –Effective address = addr. field of instr. + index register (offset) Base-register mode –Effective address = base register + addr. field of instr. (offset)

19. Addressing Modes (Summary)

20. Instruction Set Architecture RISC (Reduced Instruction Set Computer) Architectures –Memory accesses are restricted to load and store instruction, and data manipulation instructions are register to register. –Addressing modes are limited in number. –Instruction formats are all of the same length. –Instructions perform elementary operations CISC (Complex Instruction Set Computer) Architectures –Memory access is directly available to most types of instruction. –Addressing mode are substantial in number. –Instruction formats are of different lengths. –Instructions perform both elementary and complex operations.

21. Instruction Set Architecture 3 categories of elementary instructions –Data transfer instructions –Data manipulation instructions –Program control instructions