1. CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 2: Intro. to Logic Circuits Chapter 2

2. Binary Logic Circuits Logic circuits perform operations on digital signals. Implemented using electronic circuits. Binary logic circuits take only two values: –0 and 1.

3. Figure 2.1 A binary switch x1=x0= (a) Two states of a switch S x (b) Symbol for a switch

4. Figure 2.2 A light controlled by a switch (a) Simple connection to a battery S x (b) Using a ground connection as the return path L BatteryLight x Power supply S L L(x) = x

5. Figure 2.3 Two basic functions (a) The logical AND function (series connection) S x 1 L Power supply S x 2 S x 1 L Power supplyS x 2 (b) The logical OR function (parallel connection) Light L(x 1, x 2 ) = x 1  x 2 L = 1 if x 1 = 1 and x 2 = 1 L = 0 otherwise L(x 1, x 2 ) = x 1 + x 2 L = 1 if x 1 = 1 or x 2 = 1 L = 0 otherwise

6. Figure 2.4 A series-parallel connection S x 1 L Power supplyS x 2 Light S x 3 L(x 1, x 2, x 3 ) = (x 1 + x 2 )  x 3

7. Figure 2.5 An inverting circuit S x L Power supply R L(x) = x L = 1 if x = 0 L = 0 if x = 1

8. Figure 2.6 A truth table for AND and OR

9. Figure 2.7 Three-input AND and OR

10. x 1 x 2 x n x 1 x 2  x n +++ x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 x 1 x 2  x 1 x 2  x n  (a) AND gates (b) OR gates x x (c) NOT gate Figure 2.8 The basic gates

11. Figure 2.9 An OR-AND function x 1 x 2 x 3 fx 1 x 2 +  x 3  =

12. x 1 x 2 1100  f 0001  1101  0011  0101  (a) Network that implements fx 1 x 1 x 2  += x 1 x 2 fx 1 x 2,() 0 1 0 1 0 0 1 1 1 1 0 1 (b) Truth table for f A B Figure 2.10 a Logic network

13. 1 0 1 0 1 0 1 0 1 0 x 1 x 2 A B f Time (c) Timing diagram 1100  0011  1101  0101  g x 1 x 2 (d) Network that implements gx 1 x 2 += Figure 2.10 b Logic network

14. Boolean Algebra 1849, George Boole published a scheme for describing logical thought and reasoning. In 1930s, Claude Shannon applied Boolean algebra to describe circuits built w/switches. Boolean algebra provides the theoretical foundation for digital design.

15. Axioms of Boolean Algebra 1.0  0 = 01 + 1 = 1 2.1  1 = 10 + 0 = 0 3.0  1 = 1  0 = 01 + 0 = 0 + 1 = 1 4.if x = 0 then x = 1if x = 1 then x = 0

16. Single-Variable Theorems 5.x  0 = 0x + 1 = 1 6.x  1 = xx + 0 = x 7.x  x = xx + x = x 8.x  x = 0x + x = 1 9.x = x

17. Principle of Duality Axioms and theorems listed in pairs to show principle of duality. Given a logic expression, its dual is found by exchanging + operators and  operators and 0s ands 1s. The dual of any true statement is true.

18. 2- and 3-Variable Properties 10a. x  y = y  x Commutative 10b. x + y = y + x 11a. x  (y  z) = (x  y)  z Associative 11b. x + (y + z) = (x + y) + z 12a. x  (y + z) = x  y + x  z Distributive 12b. x + y  z = (x + y)  (x + z)

19. 2- and 3-Variable Properties 13a. x + x  y = xAbsorption 13b. x  (x + y) = x 14a. x  y + x  y = xCombining 14b. (x + y)  (x + y) = x 15a. x  y = x + yDeMorgan’s Thm 15b. x + y = x  y 16. x + x  y = x + yx  (x + y) = x  y

20. Figure 2.11 Proof of DeMorgan’s theorem

21. (x 1 + x 3 )  (x 1 + x 3 ) = x 1  x 3 + x 1  x 3

22. x 1  x 3 + x 2  x 3 + x 1  x 3 + x 2  x 3 = x 1  x 2 + x 1  x 2 + x 1  x 2

23. Figure 2.12 The Venn diagram representation xy z x xyxy x x x (a) Constant 1(b) Constant 0 (c) Variable x (d)(e)(f) (g) (h) xxy  xy+ xyz+  xy  y x

24. Figure 2.13 Verification of the distributive property xy z xy z xy z xy z xy z xy z x xy  xy  x+z  xyz+  (a) (d) (c)(f) xz  yz+ (b) (e)

25. Figure 2.14 Verification example xy z yx z xy z xy  yz  xy  x+z  xz  xy z xy  xy  x+zyz  +  xy z xz  y z xy z x

26. Notation x = x’ = !x = NOT x f(x 1,x 2 ) = x 1 + x 2 = (x 1 + x 2 )’ = !(x 1 + x 2 ) = NOT(x 1 + x 2 ) x 1  x 2 = x 1  x 2 = x 1 x 2 x 1 + x 2 = x 1  x 2

27. Precedence of Operations In absence of parentheses, operations are performed in this order: NOT, AND, OR. x 1 x 2 + x 1 ’ x 2 ’ = (x 1 x 2 ) + ((x 1 ’) (x 2 ’))

28. Figure 2.15 A function to be synthesized

29. f (a) Canonical sum-of-products f (b) Minimal-cost realization x 2 x 1 x 1 x 2 Figure 2.16 Two implementations of a function

30. Figure 2.17 Three-variable Minterms and Maxterms

31. Figure 2.18 A three-variable function

32. f (a) A minimal sum-of-products realization x 1 x 2 x 3

33. Figure 2.18 A three-variable function

34. f (b) A minimal product-of-sums realization x 2 x 1 x 3

35. Figure 2.20 Truth table for a three-way light controller

36. Figure 2.21 SOP implementation of the three-way light controller f (a) Sum-of-products realization x 1 x 2 x 3

37. Figure 2.21 POS implementation of the three-way light controller (b) Product-of-sums realization f x 1 x 2 x 3

38. 0000 0010 0101 0111 1000 1011 1100 1111 (a)Truthtable f x 1 x 2 s f s x 1 x 2 0 1 (c) Graphical symbol (b) Circuit 0 1 (d)Morecompacttruth-tablerepresentation sx1x1 x2x2 f (s, x 1, x 2 ) s x1x1 x2x2 Figure 2.22 Multiplexer

39. Design Entry Truth tables –Practical for only small circuits. Schematic capture –Interconnect symbols in some library. –Facilitates hierarchical design. –Good for larger circuits. –Difficult to use for very large circuits.

40. Figure 2.23 Screen capture of the Waveform Editor

41. Figure 2.24 Screen capture of the Graphic Editor

42. Design Entry (cont) Hardware description languages (HDLs). –Similar to a programming language. –VHDL and Verilog HDL are IEEE standards. –Provide design portability. –Allow for sharing and design reuse. –Support hierarchical design. –Can be combined with schematics.

43. Synthesis Logic synthesis, or logic optimization, is process to translate a truth table, schematic, or VHDL code into a network of logic gates. What makes a circuit good depends on the application. Converting logic description to a physical design entails technology mapping and layout synthesis.

44. Functional Simulation A functional simulator is used to determine if designed circuit operates correctly. User provides inputs values to the circuit. Simulator determines circuits response. User checks responses against required. A timing simulator can be used to check the performance of a design.

45. Figure 2.25 The first stages of a CAD system Design conception Truth table VHDLSchematic capture Simple synthesis (see section 2.8.2) Translation Merge Boolean equationsINITIAL SYNTHESIS TOOLS DESIGN ENTRY Design correct? Logic synthesis, physical design, timing simulation Functional simulation No Yes (see section 4.12)

46. VHDL - Very high speed integrated circuit hardware description language Original IEEE standard adopted in 1987. Revised standard in 1993. Originally used for documentation and simulation. Now, it is also used for synthesis. Very complex language, but only a subset is needed to design wide range of circuits.

47. Representing Digital Signals Each logic signal in a circuit is a data object in the VHDL code. Data objects in VHDL are assigned types. A simple type is BIT which is used for objects that can only take 2 values: 0 and 1. Other data types are introduced later.

48. Figure 2.26 A simple logic function and corresponding VHDL code f x 3 x 1 x 2

49. Figure 2.30 VHDL code for a four-input function

50. f g x 3 x 1 x 2 x 4 Figure 2. 31 Logic circuit for four-input function

51. How NOT to Write VHDL Code Novice tempted to write code with lots of variables and loops. This code style is difficult to relate to the circuit and should be avoided. Good guideline is that if designer cannot determine what circuit is doing from code, then circuit synthesized likely will be wrong

52. Concluding Remarks Introduced concept of logic circuits. –Implemented using logic gates. –Described with Boolean algebra. Briefly introduced CAD tools.